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  • 學位論文

高介電閘層金氧半電晶體之界面缺陷與氧化層電荷分佈量測研究

Measurements of Interface Traps and Depth Profiling of Border Traps in MOSFETs with High-K Gate Dielectrics

指導教授 : 張廖貴術
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參考文獻


[1] Xuguang Wang, Jun Liu, Feng Zhu, Naoki Yamada, and Dim-Lee Kwong, “A Simple Approach to Fabrication of High-Quality HfSiON Gate Dielectrics With Improved nMOSFET Performances,” IEEE Trans. Electron Devices, vol. 51, pp.
[2] P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes,Consistent Model for the Hot-Carrier Degradation in N-Channel and P-Channel MOSFET’s, ”IEEE Transactions on Electron Devices, Vol.35, 1998, p.2194.
[3] S. Tam, P. K. Ko, and C. Hu, “Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s,” IEEE Transaction on Electron Devices, Vol.31,September 1984, p.1116.
[4] Jong.Son Lyu. Kee-Soo Nam and Choochon. Lee, "Determination of interface trap density in metal oxide semiconductor field-effect transistor through
[5] Wesley L. Tseng, “A new charge pumping method of measuring Si-SiO2 interface states”, J. Appl.Phys., vol. 62, no. 2,July 1987,p.591-599.

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