- 學位論文
高介電層閘極金氧半電晶體電應力產生之界面陷阱與氧化層電荷分佈量測研究
Detection of stress-induced Interface Traps and Border Traps in MOSFETs with High-K Gate Dielectrics
摘要
為了滿足ITRS元件持續縮小化的要求，一般廣泛的認為高介電係數材料將取代原本的二氧化矽成為金氧半元件閘極介電層來改善漏電流的問題，然而在材料替換的過程中，許多問題產生，如電荷捕獲(charge trapping)，臨界電壓(threshold voltage)飄移，載子遷移率(mobility)下降等，因此應用在高介電係數閘極介電層電晶體的界面缺陷(interface traps)及氧化層缺陷(oxide traps)可靠度分析因應而生。 本論文主要的研究工作是將電荷汲引技術應用在元件的可靠度分析上面，實驗結果顯示，高介電係數閘極介電層中的弱鍵結很容易因為電應力的影響而捕捉電荷，造成起始電壓漂移，而介電層中的缺陷可能是不固定的缺陷，行為類似電洞。 此外，本篇中也討論了電荷汲引電流中的漏電流成分解決方法，以及改變閘極信號振幅的影響。 最後深入的探討量測縱深分不實的重要參數：限制因子。藉由適當的調整閘極信號偏壓高低，可以選擇電子或電洞作為量測時的限制因子。
並列摘要
Abstract To fulfill the scaling scenario as projected in the International Technology Roadmap for Semiconductors (ITRS), it is widely believed that a high-k (high permittivity) dielectric is needed to replace SiO2 as the CMOS gate dielectric to reduce significantly the gate leakage current. With the using of these alternative materials, the analyses of interface and gate dielectric quality have become important due to the higher interface states and worse gate dielectric quality. The interface states can trap electrons or holes and even the border traps can also. Trapped charge causes instabilities of electrical properties like threshold voltage shift, carrier mobility degradation and less reliability. Hence, the studies of the interface states and depth profile of border traps and trapping mechanism play a significant role in the new generation semiconductor industry. In this work, we applied charge pumping technique to reliability measurement. Experimental results indicate that the weak bonds present in high-k gate dielectric are easily trapped by charges after stress; thus, stress results in a large Vth shift. It is also demonstrated from the Nbt profile that the border trap induced by stress is probably not a fixed trapping center but a mobile defect like hole. Moreover, we discuss the tunneling component of CP current and effects of voltage swing in high-k gated MOSFETs. An effective method was proposed to eliminate the tunneling component. Finally, the limitation factor of Nbt(x) depth profile measurement was investigated. We should carefully set voltage swing and bias level to choose electron or hole as limitation factor.