- 學位論文
絕緣介電氧化層應用於摻雜析離式蕭特基金氧半電晶體
Dopant Segregated Schottky Barrier MOSFETs with an Insulated Dielectric Oxide
摘要
摘 要 雖然可以藉由高濃度的摻雜析離層這項技術，有效的調變蕭特基能障的分布來改善蕭特基金氧半元件特性。但是具備摻雜析離層的蕭特基金氧半元件相較於傳統金氧半電晶體，在短通道行為的表現上，會因摻雜析離層造成的延伸，使的元件的特性更為惡化。並且也可以觀察到，即便是有這層高濃度摻雜析離層，其雙向導通行為會隨短通道之微縮而顯著退化。如同傳統的金氧半電晶體，為了能有效去控制短通道行為，利用經過最佳化的側邊環狀佈植。可惜的是當使用了側邊環狀佈植，具備摻雜析離層的蕭特基金氧半元件呈現出嚴重且無法接受的雙向導通電洞流以及價帶至傳導帶間穿隧電流。並且當濃度提高時，情況會更為嚴重。而在具備摻雜析離層的蕭特基金氧半元件利用絕緣層覆矽晶基板這方面，也會經由埋入氧化層所產生的通道位能勢缺陷，導致額外熱發射電子流的形成，進而限制了元件的轉換特性。 因此其元件的發展仍存在許多的挑戰，為了因應具備摻雜析離層的蕭特基金氧半元件在未來繼續微縮的可能性，本篇論文提出一種具絕緣介電氧化層產生超淺延伸接面的蕭特基元件架構，解決上述所提到的問題並提高原有的元件特性。而所有研究結果都是藉由二維的模擬軟體來完成。在高濃度的摻雜析離層與環狀佈植之間，經由利用絕緣介電氧化層來隔絕後，橫向穿透電場明顯的降低並使得價帶至傳導帶間穿隧電流同時下降。除此之外，電洞蕭特基能障窄化現象的減輕，也讓雙極性電洞流降至一個對元件特性影響可忽略的程度。因此，就可以利用一個最佳化的環狀佈植來有效的控制短通道行為，而不會伴隨其它漏電流的機制。另外在此架構下，可以完全性的消除元件通道經由埋入氧化層產生電壓偶合而導致位能勢下降的現象。所以在保有高濃度的摻雜析離層其優點的同時，也能利用環狀佈植來有效的控制短通道行為，這樣顯著的良好特性，可使得摻雜析離式蕭特基金氧半元件在未來的發展上更有潛力。
並列摘要
ABSTRACT Although the dopant segregation (DS) technique can efficiently modify a Schottky barrier to improve SBMOS, the performance of scaled DS-SBMOS suffers from degraded short-channel behavior and ambipolar conduction from the extension of a heavily doped segregation layer. As in traditional MOSFETs, lateral halo profile must be used together with minimization of vertical dimensions to control efficiency the short-channel behaviors of DS-SBMOS. Unfortunately, the ambipolar hole current and the band-to-band tunneling leakage are significantly aggravated due to the parasitic N+ extension/P+ halo junction. In addition, it can be found that the degradation in subthreshold current is observed for the use of silicon-on-insulator (SOI) structure. The potential of channel region decreases due to the stronger gate control, and the potential weakness results in significant subsurface thermal emission electron current that limits the switching characteristics of SOI DS-SBMOS. An Insulated Dielectric Oxide (IDO) structure is presented for the DS-SBMOS devices to suppress the unwanted on- and off-state leakage currents in short-channel DS-SBMOS. The effects of the IDO on DS-SBMOS are investigated using two-dimensional device simulations. With sidewall IDO insulators between the heavily doped N+ segregation layer and P+ halo region, the lateral electrical field can be significantly lowered leads to band-to-band leakage currents are minimized. It also relieves the narrowing of the hole Schottky barrier in the drain region to yield a neglected ambipolar hole current. Thus, an optimal halo can be utilized to control the short-channel effect without any constraints in problematic leakage currents. Besides, the IDO structure also eliminates the potential weakness because the channel potential is not coupling via the buried oxide layer. The design of IDO DS-SBMOS combines both the merits of dopant segregation technique and ideal halo profile to serve as an attractive candidate for next-generation CMOS devices.