摘要
本篇論文探討碳化矽雙載子功率元件的製作與設計，包含了p-i-n二極體及雙載子接面電晶體。傳統的碳化矽p-i-n二極體有長期操作的可靠度問題稱作雙極劣化現象，元件順向操作時電子電洞的結合會使磊晶中的缺陷擴張，而使操作電壓上升。我們製作二極體在磨薄後的碳化矽高純度半絕緣基板上，輔以離子佈植來形成P+及N+區域，同時，利用離子佈植碳原子接著高溫趨入來提升載子生命週期，期望能解決可靠度問題。不幸地，實驗結果不如預期，當操作在40 V時，正向導通電流密度只有0.0001 A/cm^2. 在功率雙載子接面電晶體方面，模擬結果顯示若提升基極參雜濃度，犧牲些許增益，能得到較小的導通電阻，離子佈植碳原子技術也用來延長載子生命週期。實驗結果顯示最大的增益只有2，並由於基極到射極串聯電阻過大，存在一段0.4 V的偏移電壓。同時，也驗證幾何尺寸對增益的影響。
並列摘要
The thesis reports the design and fabrication of 4H-SiC bipolar devices including p-i-n diodes and bipolar junction transistors. Conventional 4H-SiC p-i-n diodes suffers from a reliability problem called bipolar degradation. It is believed that the recombination of electrons and holes in forward conduction helps the expansion of stacking faults, resulting in an increase in forward voltage. In this study, p-i-n diodes were built on a thinned high-purity semi-insulating wafer with ion implantation to form P+ and N+ regions. At the same time, carbon implantation was implanted followed by a drive-in annealing to enhance the carrier lifetime. It is expected to solve the reliability problem.. Unfortunately, the experiment results are not as expected. The current density is only 0.0001 A/cm^2 when forward biased at 40 V. In bipolar junction transistors, by increasing the base doping, a smaller on-resistance at the cost of a reduced current gain is expected from simulation. Carbon implantation technique was also used in BJT fabrication to enhance the carrier lifetime. From experiments, however, the maximum current gain observed is only 2 with a large offset voltage of 0.4 V due to a high resistance from base to emitter. The effects of device geometry on the current gain were investigated.
並列關鍵字
無資料參考文獻
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