- 學位論文
浮動閘極式記憶體閘間層邊緣效應之模型與分析
Analysis and Modeling of Edge Effect on Inter-Poly Dielectric Layer of Floating Gate Flash Memory
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摘要
邊緣效應(Edge Effect)是指氧化層邊緣因製程熱處理產生非完美的形狀，造成元件的效率降低。浮動閘極式快閃記憶體記憶體(Floating Gate Flash Memory)的閘間層(Inter-Poly Dielectric Layer)的邊緣效應發生在用一層薄氧化層修補因定義閘極而被破壞的閘間層時，在修補的過程中會因為氧氣的通入造成氧化層邊緣的增厚，造成寫入速度的降低。本篇論文主要是提供一個可以量化分析發生在浮動閘極式快閃記憶體的閘間層之邊緣效應的模型，以及與穿隧氧化層(Tunnel Oxide)的邊緣效應之比較。利用本論文所提供的模型分析與MEDICI模擬閘間層與穿隧氧化層的邊緣效應後可以發現到閘間層邊緣增厚6奈米時記憶窗減少0.3-0.9V，穿隧氧化層邊緣增厚2奈米時記憶窗就已減少了0.1V-2.2V，可了解穿隧氧化層的邊緣效應之影響還是要來的大很多。另外，在設立模型時，分成邊緣為直線形狀與邊緣為拋物線形狀，在閘間層邊緣增厚6奈米邊緣未重疊前，利用直線形邊緣分析寫入速度的變化，可以發現記憶窗比拋物線形邊緣小約0.2V，故直線邊緣會比拋物線形邊緣的模型之寫入速度的變化要大得多。而將閘間層邊緣減薄之後可以提升記憶體元件的寫入速度，閘間層邊緣減薄4奈米可以使記憶窗增加0.5-0.8V，但閘間層太薄可能導致提早寫入飽和的情形。
並列摘要
The “edge effect” means that edge of oxide would be abnormal after performing high temperature process, and the efficiency of device will degrade. Edge effect on inter-poly dielectric (IPD) layer of floating gate flash memory occurs when re-oxidation restores the damage of edge of IPD layer which is due to defining gate pattern of floating gate flash memory, re-oxidation would lead to thickening of oxide edge, and program speed of memory will become lower. The contribution of this thesis is to propose a model which can analyze edge effect on inter-poly dielectric (IPD) layer of floating gate flash memory and compare them to the edge effect on tunneling oxide. Simulation by MEDICI and proposed model shows that when IPD edge thickens 6nm, memory window reduces 0.3-0.9V; when tunneling oxide edge thickens 2nm, memory window reduces 0.1-2.2V, it shows that program speed variation due to edge effect on tunneling oxide is larger than on IPD layer. Besides, there are two shapes of edge in proposed model: linear edge and parabolic edge. When IPD edge thickens 6nm and edge encroachment is not overlapped, we adopt linear edge to analyze variation of program speed. We find that memory window is 0.2V smaller than the result which is analyzed by parabolic edge, so variation of program speed of linear edge is larger than of parabolic edge when edge encroachment is not overlapped. Thinner edge can increase program speed. The simulation shows that memory window increases 0.5-0.8V when thickness of IPD edge reduces 4nm, but too thinner edge on IPD layer could result in program saturation.
參考文獻
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