- 學位論文
以串聯GGNMOS及二極體串以增加ESD保護電壓之研究
A study on Adding Diode String to GGNMOS to Improve ESD Performance
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摘要
摘要 靜電防護一直都是設計積體電路時其中一項很重要的議題，會影響著積體電路使用上的可靠度。而靜電防護電路的功用即為，旁通從接腳進入的多餘靜電電荷以避免內部核心電路被損壞。靜電防護電路中兩項重要的設計參數分別為電流進入電流槽的能力以及觸發電壓。當電壓低於觸發電壓時，靜電防護電路應該要為關閉的狀態並且不會損耗額外的待機電流，當腳座的電壓一旦高於觸發電壓的時候，靜電防護電路應該要立即打開並且盡可能得拉入越多的電流。今日的系統單晶片發展，在一顆晶片上有多樣化的電壓源是很常見的,因此我們希望有多元的靜電防護保護電路來保護不同的電壓供應源範圍。 在當今的設計實務上，每一個靜電放電保護電路被設計成只能有一個特定的觸發電壓值，因此，為了要保護多元的電壓源範圍，多元的靜電放電防護電路必須要被發展。這篇論文提出了一個方法，可以使得有不同觸發電壓的靜電放電保護電路被從容地實踐。這個方法是將二極體串放在一個常用的閘極接地的Ｎ型金氧半電晶體上(GGNMOS)，形成一個獨立的靜電放電防護電路。藉由改變二極體串中二極體的數目，觸發電壓的大小可以被調整。因此，擁有不同觸發電壓的靜電放電保護電路可以快速有效率的發展。 使用二極體串來做靜電防護已經知道會有達林頓電路的問題存在。其中漏電流會增加共用基底的電壓，這將會降低二極體串的電壓降。但是，為了要增加靜電保護電路的觸發電壓，這個問題必須要被克服，這篇論文提出的解決方法是使用triple well來將二極體串以及GGNMOS 分開。由於之前沒有把GGNMOS放在triple well 裡面過，因此，這個議題將被全盤性的探討。這篇論文證明了使用適當的元件結構，就可以將由triple well而產生的寄生縱向雙載子電晶體的影響降到最低。因此二極體串上額外的電壓差可以完整的呈現出來。還有一個問題也已經知道會對最後的觸發電壓產生影響，這個問題是GGNMOS的電極間連結電位差的大小。為了要使待機電流在觸發之前能有最小值，GGNMOS的閘極是接地的。但是如果GGNMOS是放在二體串的前面，則VGB則會在觸發之後變為負值。這將使觸發的效率變低，以及降低堆疊的靜電防護電路的有效性。這篇論文證明了，將VGB以及VGS操作在零電位差，靜電防護的觸發電壓衰退的情形將不會被觀察到。 在這篇研究中，廣泛的元件模擬被使用來驗證這篇研究中的理論。這些模擬結果，成功的展示了當每一個二極體加入一個二極體串的時候，靜電防護的觸發電壓可以增加一個固定的量。因此，一個可以預測觸發電壓的多元靜電防護電路可以從容地被發展出來。這個方法可以促進未來在SOC的領域中，靜電防護保護電路的設計。
並列摘要
Abstract Electrostatic Discharge (ESD) has always been one of the most important reliability issues for an integrated circuit (IC) design. The principle of ESD is to use a ESD protection circuit to bypass excess electrostatic charges that come in contact with the IC pins and thus protecting the internal core circuit from damages. The important design parameters for an ESD protection circuit is the current sinking capability and the triggering voltage. Below the triggering voltage, the ESD circuit should be off and consumes no standby power. Once the pin voltage is higher than the triggering voltage, the ESD circuit is turned on to sink as much current as possible. In today’s System-on-Chip (SOC) design scenario, multiple voltage supplies are common on a single chip. Thus, it can be expected to have multiple ESD protection circuits to protect different power domains. In today’s design practice, each ESD protection circuit is designed for a specific triggering voltage. Thus, in case of protecting multiple power domains multiple ESD circuits may need to be developed. In this thesis, we propose a method that allows ESD protection circuits with different triggering voltage to be implemented with ease. This method adds stacked diodes (diode string) to a popular ESD protection device GGNMOS, grounded-gate NMOS transistor, to form the individual ESD protection circuit. By changing the number of diodes in the diode string, the triggering voltage can be adjusted. Thus, it enables fast and efficient development of ESD protection circuit with various triggering voltages. Using diode stings for ESD protection is known to have the issue of Darlington Effect, in which leakage current increases the voltage of the shared substrate that lowers the voltage drop across the diode string. This issue needs to be overcome in order to increase the triggering voltage of our ESD circuit. Our approach is to use the triple well to isolate the diode string and the GGNMOS. Putting GGNMOS in a triple well has not been studied before, thus, a thorough study is performed. We show that with proper device structures, it is possible to minimize the extra parasitic vertical bipolar transistor introduced by the triple wells. Thus, the additional voltage drop across the diode string can be fully exerted. One more issue is shown to impact the final triggering voltage, that is, the GGNMOS connection. The GGNMOS has the gate terminal grounded to minimize the standby current before triggering. If the GGNMOS is stacked on top of the diode string, the VGB can then be negative after triggering. This decreases the turn-on efficiency and reduces the effectiveness of our stacked ESD protection circuit. We show that with GGNMOS biased at zero VGB and VGS, no degradation in ESD triggering voltage is observed. In this study, extensive device simulations are performed to verify our theories. Using simulations, we successfully demonstrated that the ESD triggering voltage can be increased by a fixed amount each time a diode is added to the string. Thus, multiple ESD protection circuits with predictable triggering voltage can be developed with ease. This methodology should facilitate future ESD protection circuit design for SOC era.
參考文獻
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