- 學位論文
動態雙緣觸發正反器於低功率應用
A dynamic double edge triggered flip-flop for low power applications
若您是本文的作者，可授權文章由華藝線上圖書館中協助推廣。
摘要
在現今的積體電路設計中，減少功率的消耗是一個很重要的設計因素。而正反器在積體電路中是一個很重要的元件，它對電路的速度和功率消耗有很大的影響。在參考文獻中[3]，提到了時脈系統的功率在總功率的消耗中占了30%到60%，而時脈系統是包含時脈網路和正反器中的時脈。雙緣觸發正反器是一個可以在時脈訊號的正緣邊緣和負緣邊緣都可以鎖存數值，因此它的時脈頻率可以減少為一半，而使得明顯降低了時脈網路的功率消耗。 在這篇論文中，我們研發出一個動態雙緣觸發正反器。而和近年來提出的雙緣觸發正反器是有所不同的[3-10]，近年來提出的雙緣觸發正反器是需要在每個的時脈邊緣產生時脈脈衝訊號，而我們的雙緣觸發正反器架構只需要使用原本的時脈訊號，如此一來才能真正節省時脈的功率消耗。非同步的重置功能(reset/set)也簡單各利用了四個電晶體加到我們的雙緣觸發正反器架構上。除此之外，掃描的功能(scan)也同樣的用了兩種方法加到我們的雙緣觸發正反器的架構上，而兩種方法是不同於傳統式的掃描架構。 利用台灣積體電路公司的65奈米低功率製程，我們證明提出的雙緣觸發正反器和正緣觸發傳輸閘正反器(TGFF)在時脈功率的消耗上可以節省達到48%；而和近年來利用在時脈的雙邊緣脈衝產生器設計而成的雙緣觸發正反器[9,14]比較下，我們的雙緣觸發正反器可以在時脈的功率消耗上節省達到60%。
並列摘要
Minimizing power consumption is one of the key design objectives in today’s integrated circuit (IC) designs. Flip-Flops are important elements in integrated circuit which have a large impact on circuit speed and power consumption. It has been shown [3] that 30% to 60% of the total power is consumed by the clock system, that includes clock distribution network and flip-flops. A double edge triggered flip-flop can latch data on both positive and negative edges of the clock signal, thus, the clock frequency can be halved and significantly reducing the clock network power consumption. In this thesis, we develop a dynamic double edge triggered flip-flop. In contrast to recently published double edge triggered flip-flops [3-10], which need to have pulse signals generated for each clock edges, our flip-flop utilizes clock signal as it is and thus consumes less power. Asynchronous set and reset functions can be easily added to this flip-flop. In addition, scan function can also be added with two approaches. Using TSMC 65LP technology, we demonstrate that the double edge triggered flip-flop can save 48% of clock power as compared to the positive triggered transmission gate flip-flop; while it saves 60% of clock power compared to the dual edge triggered flip-flop [9,14] which employs a pulse generator to enable double edge trigger capability.
參考文獻
[1]M. Parsa, M. Aleshams, and M. Imanieh, "A new structure of low-power and low-voltage double-edge triggered flip-flop," in Advances in Energy Conversion Technologies (ICAECT), 2014 International Conference on, 2014, pp. 118-124.
[2]C. Mei-Wei, C. Ming-Hung, W. Pei-Chen, K. Yi-Ping, Y. Chun-Lin, C. Yuan-Hua, et al., "A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range," in SOC Conference (SOCC), 2013 IEEE 26th International, 2013, pp. 92-97.
[4]S. Balan and S. K. Daniel, "Dual-edge triggered sense-amplifier flip-flop for Low Power systems," in Green Technologies (ICGT), 2012 International Conference on, 2012, pp. 135-142.
[5]P. Myint Wai, F. Kangkang, G. Wang-Ling, and Y. Kiat-Seng, "Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1-9, 2011.
[8]C. Lih-Yih and L. Shien-Chun, "Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 17, pp. 1659-1663, 2009.