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  • 學位論文

新型一次寫入型記憶體之研究

The Study of Novel Anti-Fuse Memory Device

指導教授 : 鄭湘原
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摘要


熔絲(fuse)和反熔絲(antifuse)為電子產品中之重要的元件,其功能可做為備用記憶體(Redundancy Memory),使用於射頻電路(RF)中,及使用於安全碼(Security Code)。電子標籤之較少字碼(Low Bit Count)的資料儲存。傳統上熔絲(Fuse)以金屬熔絲(Metal Fuse)及複晶矽熔絲(Poly Fuse) 為主,寫入方式以大電流于以燒斷,此方式耗耗功率較大。而反熔絲(Anti-fuse)的結構在兩平行板導體間加入介電層,寫入時在兩導體端加一高偏壓使該介電層崩潰,此元件製造在現有的製程上需增加製程步驟。隨著元件尺寸變小,閘極氧化層的崩潰電壓隨著厚度變薄而下降,近年來已有少數公司發展出以MOS元件作反熔絲元件,這類元件寫入方式以閘極氧化層崩潰機制和穿透(punch through)機制為主。 本篇論文利用汲極端穿透機制使得汲極(Drain)到源極(Source)之通道產生永久性損壞,而成為寫入的操做方式。從實驗結果可發現用穿透機制來寫入元件比傳統上用閘極氧化層崩潰所需的寫入電壓低並能縮短寫入時間。本論文亦利用TSUPREM4 及MEDICI 分別去模擬一次寫入型記憶體元件的結構其基本電性,以及元件寫入之狀態

關鍵字

反熔絲 記憶體 一次寫入

並列摘要


Fuse and antifuse devices are important micro-electric devices. Their applications include as memory redundancy, RF circuit trimming, security code, and low-bit-count electric label. Their device structures of fuse devices are mainly metal fuse-type and poly fuse-type. They can be programmed by applying large current to melt the conductor line, and the power consumption of these programming devices is large. The structure of antifuse devices is two conductor plate sandwiched with thin dielectric material. The high voltage is supplied between two plates at programming. These devices require additional process steps. The commercial antifuse products become feasible since the gate oxide breakdown voltage is decreasing with the device shrinking. The standard MOSFET is used here for study of antifuse devices. The gate oxide breakdown mechanics and avalanche breakdown mechanics can be used for programming In this thesis, punch-through mechanics are used for programming wherein the high field causes permanently channel breakdown between source and drain terminal. The programming time and programming voltage are decreased based on this programming method. TCAD tools, TSUPREM4 and MEDICI, are used to simulate the antifuse structure, basic electrical characteristics and program behavior.

並列關鍵字

OTP Memory Anti-fuse

參考文獻


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[1-6] A. W. Longman, ”Application-Specific Integrated Circuits”
[2-1] J. H. Stathis. “Percolation models for gate oxide breakdown”,

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