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  • 學位論文

穿透效應於金氧半場效電晶體之 研究與應用

The Study of Punch Through Effect in MOSFET and Its Application

指導教授 : 鄭湘原
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摘要


熔絲(fuse)和反熔絲(antifuse)為電子產品中之重要的元件,其功能可做為備用記憶體(Redundancy Memory)。傳統上熔絲(Fuse)以金屬熔絲(Metal Fuse)及複晶矽熔絲(Poly Fuse) 為主,寫入方式以大電流于以燒斷,此方式耗耗功率較大。而反熔絲(Anti-fuse)的結構在兩平行板導體間加入介電層,寫入時在兩導體端加一高偏壓使該介電層崩潰,此元件製造在現有的製程上需增加製程步驟。隨著元件尺寸變小,閘極氧化層的崩潰電壓隨著厚度變薄而下降,近年來已有少數公司發展出以MOS元件作反熔絲元件,這類元件寫入方式以閘極氧化層崩潰機制為主。 本篇論文利用汲極端穿透(punch through)機制使得汲極(Drain)到源極(Source)之通道產生永久性損壞,而成為寫入的操做方式。從實驗結果可發現利用穿透機制來寫入元件比傳統上用閘極氧化層崩潰所需的寫入電壓低並能縮短寫入時間。本論文對寫入偏壓做最佳化及可靠度分析,亦利用TSUPREM4 及MEDICI驗證新型反熔絲一次寫入型記憶體元件的結構其基本電性,以及元件寫入之狀態。

並列摘要


Fuse and antifuse devices are important micro-electric devices. Their applications include memory redundancy, RF circuit trimming, security code, and low-bit-count electric label. The conventional device structures as fuses are mainly metal fuse-type and poly fuse-type. They can be only programmed by applying large current to melt the conductor line, and the power consumption of these programming devices is large. The common structure of antifuse devices is two conductor plate sandwiched with thin dielectric material. A high voltage is supplied between two plates for programming. These devices require additional process steps. The commercial antifuse products using thin gate oxide become feasible since the gate oxide breakdown voltage is decreasing as the device shrinks. A standard MOSFET precess is used as antifuse devices for this thesis. In this thesis, punch-through mechanics are used for programming wherein the high field causes permanently channel breakdown between source and drain terminals. The programming time and programming voltage are improved based on this programming method. TCAD tools,i.e. TSUPREM4 and MEDICI, are used to simulate the antifuse structure, basic electrical characteristics and field distribution.

參考文獻


[1-5]. D. W. Greve “Programming Mechanism od Polysilicon Resistor Fuses”, IEEE Journal of Solid-State Circuit., vol. SC-17, NO.2, pages 349-354, APRIL, 1982.
[2-5]. T. Tomita, H. Utsunomiya ” Hot hole induced breakdown of thin silicon flms” JJAP, pages 3664–3666, December 1997.
[2-7]. H.Wong “A physically-based MOS transistor avalanche breakdown model” IEEE Transaction on Electron Devices, pages 2197–2202, December 1995.
[2-9]. H.. Wong ”Modeling of the parasitic transistor-induced drain breakdown in MOSFET’s” IEEE Transaction on Electron Devices
[2-10]. H. Wong “Drain breakdown in submicron MOSFETs : a review” Microelectronics reliability, pages 3-14, July 1999

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