摘要
中文摘要 時鐘樹為影響晶片效能及功能正常運作的主要因素，隨著晶片的製程越來越進步，二維晶片漸漸面臨了瓶頸。 因此近年來已有研究將傳統的二維晶片轉換成三維垂直堆疊的晶片(3D Stacked IC)。 三維晶片能夠有效的降低元件彼此之間的連線線長，提升晶片整體的效能。 而三維晶片中，各層的晶片以垂直方向的方式堆疊在一起，造成晶片內部的溫度大幅度的增加，導線電阻也隨之上升，因此如何在考慮溫度分佈的情況下，建立一棵最小化時序差異的時鐘樹已經是現今一個重要的課題。 本篇論文提出一個以DME (Deferred-Merge Embedding)為基礎的時鐘樹構建方法。在時鐘樹建立之前，讀入晶片各層溫度分佈的情況，我們提出將Sink、Merging Segment的電容轉換為距離，產生新的座標。使用Delaunay Triangulation建立各點的連線關係，計算每個邊的cost。接著以Load-based的Grouping方法，挑選較小電容的點先合併。 挑選出的組合，我們在考慮溫度分佈下，找到Merging Segment的位置，產生新的internal nodes，再回到Delaunay Triangulation建立新的連線關係，直到只剩一個尚未合併的點為止。最後Top Down的階段根據時鐘樹拓墣的架構，由Source到樹根再到其child nodes，在各個Merging Segment上找到離其parent最近點，完成時鐘樹的建立。 由實驗結果可以發現，本演算法所建立的時鐘樹，所造成的skew，在讀入的Temperature Profile及室溫(均勻分佈)Profile下，所有case的skew差都小於2 ps。 與TACO比較時，TACO的worst skew為我們的四倍。
並列摘要
Abstract The clock tree has been the main factor of the performance and the correctness of functionality of a chip. With increasingly advancement of the manufacturing process, two dimensional ICs can not follow the prediction of Moore's Law. Therefore, there are many researches on how to transform the traditional 2D ICs into the three dimensional ICs in recent years. Three dimensional ICs can reduce the wirelength efficiently, and increase the performance of a chip. The impact of the skew in a clock tree becomes more and more important, because the latency is decreased at current manufacturing process. Heat can not be dissipated efficiently in three dimensional ICs, because each chip is stacked in vertical direction. The temperature in three dimensional ICs increases drastically. The wire resistance increases with the temperature. Therefore, how to construct a minimal skew clock tree considering the temperature distribution is becoming an important issue. This paper proposed a clock tree generator based on Deffered-Merge Embedding (DME) method. First, we import the temperature distribution of a chip before we construct the clock tree. We can build up our clock tree topology according to the temperature distribution, and choose a proper L-path to avoid the hot spots. In DME bottom up phase, we will calculate the precise position of Merging Segments according to the temperature at each tile. Finally, we build up the thermal-aware clock tree in top down phase with the information of the topology. The experimental results show that, our algorithm can construct a balanced skew clock tree. The skew of the clock tree under worst case temperature profile and the room temperature profile(uniform distribution) is nearly equal. The skew difference all less then 3 ps in all cases. And compared with TACO, the worst skew of TACO is 4X than us averagely.