- 學位論文
扁平式導線架封裝方式之研究以DRAM封裝為例
A Study Of Flate Leadframe Packaging By Way Of Dram Package
摘要
摘要 由於消費者對市場電子產品多功能、小尺寸之要求，以基板為主材料之塑料格柵式封裝(PBGA)已成為現行封裝主要方式之一，其簡易的封裝製程及接近晶片大小尺寸為其主要優點，且較短的線路亦達成了晶片的效能需求；唯其基板材料之性質及加工之特性，對於生產中保存及成品使用環境中溫濕度變化，易造成品質、使用壽命、工作信賴性等方面之不良影響；本文即以此為研究重點，期能於現有封裝製程能力及設備中，獲得改善的方法。 在電腦產業中，DRAM始終是不可或缺的關鍵零組件。本文即以廣泛使用DDRII記憶體之封裝為例進行探討，從文獻中瞭解記憶體之演進及原理，自初期的DIP到現在BGA封裝產品發展中，針對採用導線架及樹脂基板封裝在電性上之差異及原因做分析；期間發現後製程的溫度變化亦為IC破壞主要因素之一，因此本研究亦將其列入關鍵因素做探討。 為符合晶片級封裝(CSP)之趨勢，本文以DDRII現用之WBGA60L封裝外觀尺寸及引腳數為依據，嘗試以直線方式取代TSOP引腳之海鷗式設計，以縮短導體線路的距離，同時避免其因斷面變化造成之反射干擾(Reflection Noise)；為克服串音干擾(Cross talk noise)現象，而採用共面接地方式，於引腳及晶片間增加一層導線架，同時可輔助其強度及引腳間距；在結構強度之考量方面，則以ANSYS做封裝後變形之模擬分析；最後再以JEDEC標準和業界所用失效模式之分析項目為主，進行改善後封裝型態之可行性確認。 本文中所研擬之封裝方式，經吸濕及彎曲等環境測試，雖能達成業界製程需求之標準，但於製作中發現有封膠氣泡及上板易造成短路等二項製程問題，因此根據異常現像及製程參數做DOE分析得到最佳封膠製程參數，消除氣泡之問題；並於導線架製程中增加交錯防銲薄膜，以避免焊錫短路問題。最後進行製程中檢驗，其結果亦可達到JEDEC標準。
並列摘要
Abstract Subject to all electronic products to market "light, thin, short, small, full-function" and other requirements, Plastic Ball Grid Array (PBGA) package has become the main form of one of its simple packaging assembly. The major advantages of Chip Scale size, shorter layout also reached the performance of the chip demand; but substrate had quality lifetime and reliability issue by environmental impact in processing and used.This paper is to focus on the method of improvement in the period to the existing package process capabilities and equipments. In the computer industry, DRAM has always been an integral part of key component. This thesis widely uses DDRII memory of the package as an example to explore the evolution of memory and principles. The difference between using lead-frame and plastic substrate of the package from DIP to BGA package products is investigated. The temperature change as one of the main failure factors in backend assembly process is also studied. To comply with the CSP of the trend, it is attempted to replace the gull-pin TSOP design and to shorten the distance between conductor lines by using the WBGA60L DDRII appearance package size and pin count based on a straight line while avoiding cross-section due to changes in its reflection noise. Used ground plane to overcome the Cross talk noise. Increased the pad in the chip and lead-frame can strengthen its strength and lead spacing. ANSYS is used to simulate the deformation of the package. Finally, the JEDEC standards pattern is used to check the reliability. In this thesis, the packaging method is examined by standard moisture and bending testing. However, there are void and short circuits problems in production, which can be solved by searching the optimal molding parameters and increasing interlaced solder masker into lead-frame process baed upon the DOE analysis. Through the quality inspection, the outcomes can achieve the JEDEC standard.