應用於環景系統之影像拼接晶片設計

本論文提出以硬體為導向的影像拼接演算法應用於汽車環景系統上，並以積體電路實現了特徵點檢測、描述符建構以及特徵點匹配三個部分。現今雖然有許多高品質輸出的影像拼接演算法，但要達到高品質影像拼接結果往往複雜度都較高，要達到即時性較為困難，因此以維持品質且低複雜度為設計的目標，提出之影像拼接演算法包含五大部分：特徵點檢測、描述符建構、特徵點匹配、影像校正及影像融合技術。為了能讓此次設計在積體電路實現，使用改進過的ORB 演算法實現特徵點檢測和描述符建構，降低了運算量以及硬體的使用量，影像融合的部分則是採用簡化後的最佳接縫搜索演算法加上選擇性模糊化演算法，不僅能降低複雜度又能維持原有的拼接影像品質這兩個設計目標。與之前的相關研究文獻比較，本論文提出之影像拼接演算法在不降低品質的條件下具有較低的複雜度及較少邏輯閘數的特性。此外，從結果可以看出，與現今高品質的商業軟體有相似的拼接影像。在硬體的部分，本論文以共用相同的採樣模型來建構描述符，取代原本演算法中難以實現成硬體的部分，大幅的降低了硬體面積，此共用採樣模型硬體架構有效的降低約75%之邏輯閘數，不僅有更低的硬體成本，還能維持原有的匹配精確度。本論文中特徵點檢測、描述符建構以及特徵點匹配這三個部分採用台積電0.18-μm CMOS 製程製作出兩顆晶片，第一顆晶片實現特徵點檢測及描述符建構兩個部分，晶片面積為615,624μm2，最高工作頻率為100MHz，功率消耗為10mW，第二顆晶片實現描述符建構及特徵點匹配的部分，晶片面積為460,302μm2，最高工作頻率為56MHz，功率消耗為1.2mW。

關鍵字

晶片設計；影像拼接

並列摘要

This thesis proposes a hardware-driven image stitching algorithm for the vehicle surrounding view system and achieves the very large scale integration (VLSI) of three parts： Feature point detection, descriptor construction, and feature point matching. Although there are many stitching algorithms for highquality stitching images, it is more complicated to achieve high-quality splicing results, and it is difficult to achieve real-time stitching. The proposed algorithm design has the characteristics of high quality and low complexity, including feature points detection, descriptor construction, feature matching, image calibration, and image fusion. An improved ORB algorithm, a simplified optimal seam algorithm, and a Partial fuzzification algorithm is proposed to this thesis. Compared with other studies, this thesis has the characteristics of lower complexity and fewer gate counts without reducing the quality and even has similar performance with the commercial software. In hardware, this thesis uses sharing the same sampling model to construct the descriptor. The circuit architecture proposed in this paper productively reduces the gate counts by 75%, with high-quality and low-cost image stitching properties. This circuit architecture not only has lower hardware costs but also maintains the original matching accuracy. In this thesis, the three parts of feature detection, descriptor construction, and feature point matching are made using TSMC’s 0.18-μm CMOS process to produce two chips. The first chip realizes two parts： Feature point detection and descriptor construction. This chip area is 615,624μm2, the operating frequency is 100MHz, and the power consumption is 10mW. The second chip realizes two parts：Descriptor construction and feature matching. This chip area is 460,302μm2, the operating frequency is 56MHz, and the power consumption is 1.2mW.