摘要
在同步序向電路中，時鐘訊號用於定義資料轉移之相對時間參考依據。而所謂的時序差異則定義為從時鐘源至暫存器止，最大之路徑延遲差異。既然時序差異對效能的影響舉足輕重，許多探討時序差異控管之研究一直以來都是討論的要點。 在深次微米時代，製程技術不斷進步，除了面積最小化、效能最佳化以及低功率消耗外，穩定度也是重要的設計目標。本論文探討高穩定度之時鐘設計策略，並提出兩個方式如下所示。 第一，我們談論降低峰值電流的時鐘設計方法。多定義域(Multi-domain)時序差異排程可用於排程每個暫存器的時脈到達時間，以致於避免暫存器同時被切換(因此造成峰值電流)。然而，求解多定義域時序排程是一個相當耗時的問題。在本論文中，我們提出幾個有效的技術用於改善求解的時間，其中包括(1) ASAP及ALAP的時序排程(用於刪除不影響最佳結果的變數)，以及(2) Zone-based 時序排程(將變數分割成數個小的變數求解區塊)。我們的實驗結果顯示我們的方法可以有效的降低求解時間。 第二，我們提出一個時鐘設計策略用於解決在閘控時鐘樹(Gated Clock Tree)中，由於負偏壓不穩定效應(Negative Bias Temperature Instability, NBTI)，而導致的時序差異問題。閘控技術的主要概念為關閉電路中處於非“致能”模式下的電路，因此電路的功率消耗可以被改善。但是由於不同的延遲老化造成的老化時序差異(Aging Skew)，設定同一層致能訊號的激活機率(Active Probability) 為一致，雖然是一個簡單降低老化時序差異的方法，但卻造成相當大的消耗功率。在本論文當中，我們開發一個Critical-PMOS-Aware的設計策略，用以減少真正需要處理及補償的PMOS的激活機率。實驗結果顯示我們的方法是一個非常有效的技術能夠解決這個問題。
並列摘要
In a synchronous sequential circuit, the clock signal is used to define a relative time reference for the movement of data. The clock skew is the maximum difference among the clock latencies (i.e., clock delays) from the clock source to flip-flops. Since the clock skew is crucial to performance, a lot of research efforts have been made to the management of clock skew. In the era of deep sub-micron, the manufacturing technology keeps growing. In addition to area minimization, performance optimization, and low power consumption, reliability is also a serious issue. In this dissertation, we study high-reliability clock design methodology. Two clock design approaches are presented below. First, we study the clock design for peak current reduction. Multi-domain clock skew scheduling can be used to arrange the arrival time of every register to avoid registers switching at the same time. However, solving this multi-domain clock skew scheduling is a very time-consuming problem. In this dissertation, we propose several efficient techniques to improve the run time. Our works includes (1) ASAP and ALAP skew scheduling (to reduce the variables without pruning the optimal solutions), and (2) Zone-based skew scheduling (to separate the variables into several smaller zones). Our experimental results show that our approaches can reduce the run time significantly. Second, we propose a design methodology to minimize the skew caused by NBTI effect in a gated clock tree. The main idea of clock gating is to shutdown the portions of circuit which are not in ‘active’ mode so that the power consumption can be reduced. Different active probabilities of clock gates cause different delay degradations. Setting the active probabilities of enable signals at the same level to the same value is an easy way to eliminate the aging skew. However, it requires a lot of power consumption. In this dissertation, we develop a critical-PMOS-aware design methodology to reduce the number of critical PMOSs, which are the necessary part to deal with and to compensate the active probability. Experimental results show that our approach is a very useful technology to solve this problem.