- 學位論文
結合具有離散和連續調頻功能的振盪器之整數型鎖相迴路
Integer-N Phase-Locked Loop Integrating an Oscillator with Both Discrete and Continuous Frequency Modulation Functions
摘要
本篇論文採用TSMC 0.18-μm CMOS 1P6M製程，設計一個結合具有離散和連續調頻功能的振盪器之整數型鎖相迴路，其電路架構包含具有啟動重置(Power-on reset)功能的相位頻率檢測器、相位頻率檢測器和電荷汞的介面電路、Constant-gm偏壓電路、使用誤差放大器進行電流補償的電荷汞、輸出擺幅設定電路、二階迴路濾波器、具有3-bits二進位權值(Binary-weighted)電容陣列的互補式交叉耦合對LC壓控振盪器、除數為128的TSPC除頻器、壓控振盪器中電容陣列的控制電路。 壓控振盪器的量測結果顯示調頻範圍為2.24 GHz~2.66 GHz (17.14%)；在100 kHz偏移處，相位雜訊為 -87.64 dBc/Hz ~ -93.66 dBc/Hz；不包含輸出緩衝器的功耗為975 μW；FOM為176.1 dB~181.4 dB。鎖相迴路的量測結果顯示頻率鎖定範圍為2.24 GHz~2.64 GHz (16.39%)；在100 Hz~100 MHz的偏移頻率範圍內，RMS jitter為10.304 psec ~ 12.700 psec；不包含輸出緩衝器的功耗約為3 mW；當鎖相迴路之輸出頻率為2.4 GHz時，在100 kHz偏移處，相位雜訊為 -85.64 dBc/Hz；參考突刺小於 -63.18dBm。 本篇論文還有分析鎖相迴路中的不同雜訊來源造成的相位雜訊。模擬結果顯示在電源存在雜訊的情況下，相位頻率檢測器和電荷汞是相位雜訊的主要來源，並且模擬結果與量測結果高度吻合。
並列摘要
This paper utilizes the TSMC 0.18-μm CMOS 1P6M process to design an integer-N phase-locked loop integrating an oscillator with both discrete and continuous frequency modulation functions. The circuit architecture includes a phase frequency detector (PFD) with power-on reset function, an interface circuit between the PFD and the charge pump, a constant-gm bias circuit, a charge pump with current compensation using an error amplifier, an output swing setting circuit, a second-order loop filter, a complementary cross-coupled LC voltage-controlled oscillator (VCO) with a 3-bit binary-weighted capacitor array, a divide-by-128 TSPC frequency divider, and a control circuit for the capacitor array in the VCO. The measurement results of the VCO show a tuning range of 2.24 GHz to 2.66 GHz (17.14%), phase noise at a 100 kHz offset is -87.64 dBc/Hz to -93.66 dBc/Hz, power consumption excluding the output buffer is 975 μW, and the Figure of Merit (FOM) is 176.1 dB to 181.4 dB. The measurement results of the Phase-Locked Loop (PLL) show a frequency locking range of 2.24 GHz to 2.64 GHz (16.39%), RMS jitter in the 100 Hz to 100 MHz offset frequency range is 10.304 psec to 12.700 psec, and power consumption excluding the output buffer is approximately 3 mW. When the PLL output frequency is 2.4 GHz, the phase noise at a 100 kHz offset is -85.64 dBc/Hz, reference spur is less than -63.18 dBm. This paper also analyzes the phase noise caused by different noise sources in the PLL. Simulation results indicate that in the presence of power supply noise, the phase frequency detector and charge pump are the main sources of phase noise, and the simulation results are highly consistent with the measurement results.