利用高阻抗線補償含信號連通柱殘段之多層印刷電路板貫穿孔訊號連通柱之阻抗不連續

Compensation for impedance mismatch of plated through-hole vias with via stubs in multilayer PCBs by using high-impedance lines

王鼎鈞(Ding-Jun, Wang)

指導教授 ： 薛光華

中原大學/電機資訊學院/通訊工程碩士學位學程/碩士(2017年)

https://doi.org/10.6840/cycu201700703

摘要

本論文研究在多層印刷電路板(PCB)中，傳輸線訊號透過訊號連通柱進行傳輸，而未使用的連通柱則會形成殘段，造成頻域反射波形|S11|、頻域穿透波形|S21|與時域反射波形(Time-Domain Reflection)的影響，首先提出訊號連通柱之影響為電容效應，使阻抗下降，因此使用高阻抗線來達到阻抗匹配之效果，因走線會隨著製程或其他需求走在不同層，因此本論文針對不同走線層使用Q3D模擬軟體設計出阻抗設計圖表，根據不同傳輸線阻抗對應不同繞線角度，再使用HFSS模擬軟體繪製結構，整理結果並驗證此方式與理論是互相印證的，除了單根結構外，也有針對差模結構不同阻抗設計圖表，不管對於頻域波形或是時域波形上皆有明顯改善，提升其訊號完整性。

關鍵字

高阻抗線補償結構 ； 訊號連通柱 ； 阻抗不連續 ； 多層印刷電路板

並列摘要

This paper is studied in multilayer printed circuit board (PCB), the transmission signal line is transmitted by signal via, while the unused connecting signal via will form a stub, it will influence Frequency-Domain Return Loss |S11|, Insertion Loss |S21|and Time-Domain Reflection (TDR).First of all, we propose the effect of signal via is the capacitance effect that the impedance drops, so we use the high-impedance transmission line to achieve impedance matching. Because the wiring is conducted on different levels in accordance with the proposes and other requirements, so that this paper use the simulator Q3D to design the impedance design chart, according to different transmission line impedance corresponding to different routing angle, and use the 3-D full-wave simulator HFSS to draw the structure, finishing the results and verifying that this and the theory are mutually confirmed. Except for a single structure, there are also different impedance design charts for differential mode structures, regardless of the Frequency-Domain waveform or Time-Domain waveforms are significantly improved, enhance its signal integrity.

並列關鍵字

high-impedance lines ； signal via ； impedance mismatch ； PCBs

參考文獻

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