摘要
本論文提出一種牙科疾病與道路缺陷偵測智慧影像處理晶片與系統設計，主要可分成三個部分，分別為醫學輔助系統之基於卷積神經網路進行牙科多種病症辨識、基於智能道路缺陷識別車規FPGA系統以及低功耗與微型化可調式數位濾波器。其中在醫學輔助系統包含了影像分析處理、影像增強與校正以及人工智慧研究。本研究在辨識病徵辨識的所有牙科問題準確率都在 90% 以上。與現有識別技術相比，最高增幅分別為13.14%和1.34%。而在車規嵌入式系統的開發中，利用Xilinx ZCU104平臺與採用 YOLOv3 進行即時坑洞偵測之實現。本研究所建立之系統能夠以FPGA平台進行即時坑洞偵測，其執行速度為27.8 FPS，並在維持平均精度的情況下，成功壓縮39.8%的實時坑洞檢測系統的大小，符合車輛即時處理與應用之需求。此外，在可調式數位濾波器中，本設計利用暫存器儲存係數，並利用係數實現有限脈衝響應的數位濾波器架構，透過暫存結構之係數儲存單元可以容易整合於其他電路實現軟韌體調整濾波頻段之功能，達到可調式濾波器的目標。 硬體方面，本論文以複雜度低的演算法及管線化架構實現可調式數位濾波器，並以台積電0.18微米製程實現晶片。晶片操作頻率為50MHz，功率消耗為241.7mW，並於晶片在設計上利用FIR運算公式的簡化，將整體架構所需之乘法器數量減少一半。晶片核心面積大小和邏輯閘數目分別為3,402.52 × 3,397.6 μm2和586,680個。
並列摘要
This study proposes a smart chip and system design for detecting dental diseases and road defects using image processing. The system includes a low power consumption and miniaturization adjustable digital filter, an automotive FPGA system for recognizing road defects, and a dental disease automatic identification system based on a convolutional neural network. The medical auxiliary system includes an image analysis, an enhancement, a correction, and an artificial intelligence research. This study has achieved over 95% accuracy in identifying all dental diseases based on symptoms, with an increase in identification technology by 13.14% and 1.34%, respectively. In developing the embedded system for automobiles, the Xilinx ZCU104 platform and YOLOv3 are utilized for real-time pothole detection. The established system can perform real-time pothole detection on the FPGA platform at an execution speed of 27.8 FPS while successfully compressing 39.8% of the size of the real-time pothole detection system. Besides, this design employs temporary registers to store coefficients and realizes the digital filter structure of the finite impulse response through the usage of coefficients. The coefficient storage unit facilitates easy integration into other circuits, allowing for adjustable filter functionality by modifying the filter frequency band through software and firmware. This research creates an adjustable digital filter using a low-complexity algorithm and a pipelined architecture in terms of hardware. The chip is manufactured using TSMC 0.18-μm technology. The operating frequency of this chip is 50MHz, and its power consumption is 0.25 mW. The proposed chip design uses the simplification of the FIR calculation algorithm to cut the number of multipliers required by the overall structure in half. The chip core area and logic gate counts are 3,502.52 × 3,497.6 μm2 and 586,680, respectively.