- 學位論文
迴轉率提升電路之設計與實現
Design and Implementation of Slew-Rate Enhancement Circuits
摘要
在現今科技日新月異之下，大部分電子電路的應用對於生活是不可或缺的，隨著製程的進步體積越來越小，積體電路也朝向速度快以及功耗低趨勢設計，為了可以達到低功耗目的，使用次臨界區(弱反轉區)已成為目前設計方法。在低電壓情況下設計也必需達到相關規格值，例如：直流增益(DC gain)、增益頻寬(Gain bandwidth)、相位裕度(Phase margin)或是迴轉率(Slew rate)。 本論文使用TSMC 0.18um 1P6M CMOS製程實現CMOS OTA，滿足一個低功耗、高迴轉率和高增益工作在次臨界區的多級放大器。本文分析折疊疊接放大器的結構與特性，針對其中電路架構以及偏壓電路加以分析，進行模擬以及驗證。提出低功耗放大器加入迴轉率增強電路檢測內部節點電壓，提供電流給輸出端達到電路操作變快，幾乎不需要額外功耗。電路設計使用1V電源供應，當驅動為200pF高負載電容時模擬結果直流增益為94.38dB，頻寬為10.4kHZ，功率消耗255.35nW，迴轉率3.810/-2.5(mV/μs)。
並列摘要
Nowadays, with the rapid development of science and technology, the application of most electronic circuits is indispensable to life. With the progress of manufacturing processes, the volume is getting smaller and smaller, and the integrated circuits are also designed for fast speed and low power consumption. In order to achieve low power consumption, the use of subthreshold regions (weak reversed regions) has become the current design method. In the case of low voltage, the design must also meet the relevant specifications, such as: DC gain, Gain bandwidth, Phase margin, or Slew rate. This paper uses TSMC 0.18um 1P6M CMOS process to achieve CMOS OTA, to meet a low-power, high slew rate and high-gain multi-stage amplifier operating in the subthreshold region. This paper analyzes the structure and characteristics of folded spliced amplifiers, analyze circuit architecture and bias circuit for simulation and verification. A low-power amplifier is proposed to add a slew-rate enhancement circuit to detect internal node voltages, provide current to the output terminals to achieve faster circuit operation, and almost no extra power consumption is required. Circuit design using 1V power supply. When the load capacitance is 200pF, the simulation result DC gain is 94.38dB. The bandwidth is 10.4kHZ. The power consumption is 255.35nW, and the slew rate is 3.810/-2.5(mV/μs).