- 學位論文
單邊非重疊離子佈植式金氧半場效電晶體內之寄生BJT崩潰與MOS擊穿機制的特性研究
Characterization of Parasitic BJT Breakdown and MOS Punch Through in Single-sided Non-Overlapped Implantation MOSFETs
摘要
在半導體工業快速蓬勃的發展之下，記憶體依功能的不同在結構上有著不同之形式。其中以非揮發性記憶體作為反熔絲元件是一種藉由改變其導電特性，由高電阻(不導電狀態)變為低電阻(導電狀態)之半導體裝置，屬於電阻式之非揮發性記憶單元，利用改變記憶單元之電阻大小達成儲存0或1等資料之目的。 研究中以單邊非重疊離子佈植式金氧半場效電晶體作為反熔絲元件之應用，目的在於深究以通道擊穿機制作為寫入操作下，崩潰效應將由MOSFET崩潰亦或是寄生BJT崩潰所主導。其中得知該元件於寫入前後擁有一超過9個數量級之電流差異。 本文最終透過實際量測資料帶入公式模型計算，並將環境溫度上升對上述兩崩潰效應做探討。由結果得知在室溫的情況下，該元件於寬度為1μm且有效通道長度大於0.19μm之通道擊穿機制將由MOSFET崩潰所主導；然而，以有效通道長度0.25μm為例，環境的溫度上升將使得該元件之寄生BJT效應加劇，從實驗與公式推導之數據顯示當環境溫度到達102°C時，通道擊穿操作所造成的基極電位抬升將達到0.6V，並使其寄生BJT操作於順向主動區，進而導致擊穿電壓於高溫的情況下驟降，故於高溫環境下尚需考慮此效應之影響。
並列摘要
Semiconductor memories develop different structures to cater to various functions under the semiconductor industry fast development nowadays. Non-volatile memory has been the application of the anti-fuse cell, which is coded by altering the high resistance (or non-conductive) state into the low resistance (or conductive) state representing the logic data “0” or “1”. The goal of this thesis is to investigate the punch-through breakdown mechanism under various ambient temperatures between MOSFET breakdown and parasitic BJT breakdown for Single-sided Non-Overlapped-Implantation (SNOI) as the anti-fuse cell. In the channel punch-through measurement, the results show a positive correlation between channel length and channel punch-through voltage. Furthermore, the n-SNOI MOSFET punch-through mechanism has been found that MOSFET breakdown dominants compared to the parasitic BJT breakdown as channel effective length less than or equal to 0.19μm at room temperature. Finally, the punch-through measurement on n-SNOI devices with W/L=1/0.25 (μm) for various ambient temperatures can be found that the parasitic BJT activation affect the punch-through breakdown as the ambient temperature increasing to 102°C, wherein the VB rises up to 0.6V during punch-through measurement.