- 學位論文
尿液導電度感測器之前端積體化讀出電路設計與實現
Design and Implementation of Front-end Readout Chip for Urine Conductivity Sensor
摘要
本研究係針對尿路結石症之尿液導電度參數前端讀出電路進行積體化電路設計與實現，研究中以多頻率阻抗/導電度量測法為基礎，由方波經濾波器消除基頻諧波產生一交流定電流，輸入至具有待測溶液的自製金四電極感測器，而由放大器訊號讀出並抑制雜訊，最後將電壓/流得出其阻抗。而本研究可分為兩大架構：在電路板驗證，以定值轉導補償方式來提高放大器共模拒斥比之特性，以符合使用一般分離式元件來實現讀出電路所需之規格。在積體化開發上，以放大器作為子電路區塊，在儀表放大器上使用3-opamp架構，共模拒斥比具有90dB的表現，在四階低通濾波器設計上，採用切換式電容組態，文中還使用與溫度成正比之電流源的補償方式來實現高穩定低頻振盪器以提供系統所需的時脈週期訊號，在監測系統驗證上使用Excel軟體與Holtek ARM開發板來實現訊號的讀取與分析。 在積體電路實現上，使用UMC 0.18um 1P6M製程進行模擬與下線製作，讀取晶片面積約0.45mm2，操作電壓為3.3V，時脈訊號為280kHz，低通截止頻率為2.88kHz，導通帶增益為40.4dB，動態功率消耗約10mW。
並列摘要
The research is aimed at the design and implementation of the integrated front-end readout circuit for sensing urine conductivity. The method is based on multi-frequency electrical conductivity. The constant sinusoidal current source is obtained using active filter converts the input pulse width modulation to sinusoidal current. Self-developed gold coated 4-electrode sensor is used while sinusoidal current is applied to outer probes and the voltage is measured from inner probes, for measurement of voltage and current are similar and only the amplifiers gain are adjusted according to input signal range. In this study, the system can divided into two structures: The amplifier used constant gm compensation circuitry to conform with high common-mode rejection ratio characteristic of readout circuit which is implemented by discrete components. For integrated readout circuit design, the used instrumentation amplifier consists of three op-amps and with 90-dB CMRR. The fourth-order lowpass filter is designed by single-end differential switched capacitor configuration. In addition, this work also propose a high stable, low frequency oscillator, that is using IPTAT current to compensate the temperature and process effect, to provide the clock signal for readout circuitry. Finally, the system is verified by Excel and Holtek ARM developed board and do collation of measuring results. The integrated readout circuit is simulated and implemented by using UMC 0.18um 1P6M process with 0.45mm2 chip size. The readout chip is operated in 3.3V supply voltage and 280kHz clock frequency. The circuitry lowpass cutoff frequency is design at 2.88kHz and with 40.4dB gain in passband. The dynamic power consumption is around 10mW.