- 學位論文
使用全線性控制範圍VCO操作於1.8伏特時脈資料回復電路之設計
1.8V Clock and Data Recovery with Full Linear Control Range VCO
摘要
時脈與資料回復電路（CDR）在通訊系統接收器應用中，佔據了相當重要的地位。近年來，更以高速度、低功率的時脈資料回復電路為主要研究趨勢。在本論中，我們提出全線性控制範圍的壓控振盪器(VCO)，來實現一個電源電壓1.8V操作在1.25Gbps的全速率時脈與資料回復電路。這個改良的延遲單元，使VCO的控制電壓範圍延伸為0~1.8V，改善VCO的頻率-電壓特性曲線的線性度，因此非常符合低電壓操作使用。壓控震盪器的模擬結果得到頻率範圍從0.88GHz到1.63GHz，抖動的峰對峰值為60ps，VCO電路的功率消耗為19.61mW，包含Buffer的VCO功率消耗為47.75mW，相位雜訊為-108dBc/Hz，CDR抖動量為310ps，此電路使用TSMC 0.35μm 2P4M CMOS 製程，佈局為271.15μm×199.95μm，為了測試方便，晶片中還包含了一個1.25GHz的鎖相迴路和亂數資料產生器。另外，我們使用Matlab Simulink建立模型分析電路穩定度以及電路可行性。
並列摘要
Clock and data recovery (CDR) circuit plays an important role in the receivers of communication applications. In recent years, high data rate and low power consumption become the main research issues of CDR. In this thesis, we proposed a 1.8V 1.25Gbps full rate CDR with full linear control range VCO. The delay cell of the VCO is modified to extend the linear controlled voltage range from 0V to 1.8V. Hence it is very suitable for low voltage operation. The simulation result shows that the oscillating frequency range of VCO is from 0.88GHz to 1.63GHz. The VCO power consumption is 19.61mW without buffer and 47.75mW with buffer. The phase noise of the VCO is -108dBc/Hz. The jitter of the CDR is 310ps. The circuit is implemented using TSMC 0.35μm 2P4M CMOS technology. The chip core area is 271.15μm 199.95μm. For testing purpose, the chip is also including a 1.25GHz PLL and a PRBS. Besides, we used MATLAB Simulink to establish the model for analyzing the stability and feasibility of the circuit.