- 學位論文
低複雜度STBC-OFDM系統之FPGA實現
FPGA Implementation of Low Complexity Scheme for STBC-OFDM System
摘要
空時區塊編碼(Space Time Block Code, STBC)被廣泛的應用在提高無線通訊系統的性能，是空間多樣(Spatial Diversity)中一個廣受矚目的技術。STBC結合正交分頻多工(Orthogonal Frequency Division Multiplexing, OFDM)的多輸入多輸出(Multiple Input Multiple Output, MIMO)無線通訊系統，使STBC可以有效地應用在更實際的無線通訊的環境，但此系統必須搭配多個反快速傅立葉轉換(Inverse Fast Fourier Transform, IFFT)與快速傅立葉轉換(Fast Fourier Transforms, FFT)電路做運算，其複雜度會隨著天線與子載波個數增長，增加了系統的計算負擔與成本。因此本論文提出一個只需單一IFFT/ FFT的低複雜度架構，使IFFT/FFT電路的個數不會隨著傳送與接收天線的個數增加而增加，因而能夠減少硬體複雜度。本論文以可程式邏輯閘陣列(Field Programmable Gate Array, FPGA)實現電路以驗證此一低複雜度架構的系統，結果顯示所提出的設計架構在硬體消耗上有顯著的下降，在傳送與接收天線各為兩根的情況與其他架構進行比較， FPGA晶片中所使用的總邏輯元件與總暫存器可以節省約48%，總記憶體使用量減少約20%，乘法器則減少50%。
並列摘要
Space-time block codes (STBC) are considered as one of the prominent technologies for spatial diversity, which is widely used to improve wireless communication system performance. A multiple input multiple output (MIMO) wireless system benefits well from the combined technology of OFDM and STBC. However, an OFDM system with STBC needs multiple inverse fast Fourier transform (IFFT) / fast Fourier transforms (FFT) and subsequently poses an adverse effect on system computational load as the number of antennas and sub-carriers grows. Therefore, in this thesis we employ a low complexity scheme with single IFFT/FFT for STBC-OFDM system. An implementation of multiple transceivers on field programmable gate array (FPGA) has shown that the hardware complexity is significantly reduced without any adverse effects on system performance. In the case of two transmitters and two receivers, the number of logic elements and registers are reduced by about 48%, the memory and the number of multipliers is reduced by about 20% and 50%, respectively.