陣列式阻抗讀取電路與顯像系統整合之研究

Research of System Integration for Impedance Array Readout Circuit and Visualization

黃偉誠(Wei-Cheng Huang)

指導教授 ： 孫台平

國立暨南國際大學/科技學院/電機工程學系/碩士(2014年)

摘要

讀取電路是作為前端感測器與後端系統介面重要的傳遞橋樑，讀取電路的架構與性能關係著訊號的品質、讀取感測器的類型、與讀取訊號的範圍等，而最重要的關鍵技術在於像素電路的設計;為了實現陣列式的讀取電路，像素電路的微小化與訊號依序輸出控制設計等，是陣列式讀取電路設計的重點。
　　為了讓電路有更多元的讀取類型，更廣泛的讀取範圍，像素電路分為兩部分設計，一部分為電流陣列讀取電路，一部分為阻抗讀取電路；在電流讀取電路部分，使用緩衝放大器注入型(Buffer direct injection, BDI)搭配電容式轉阻放大器(Capacitive Transimpedance Amplifier, CTIA)組成雙模像素電路架構。BDI模式是利用放大器回授達成降低輸出阻抗並提升注入效率，用來處理感應電流較高的感測器；CTIA模式不需要額外偏壓控制感測電路，適用於感應電流小的感測器。由於BDI與CTIA兩種電路架構中皆有使用運算放大器，為了使像素能微小化與降低耗能，採用兩個電路架構共享一個運算放大器，並搭配開關實現四種讀出模式。阻抗讀取電路部分，採用共源極電路作為像素電路，可偵測阻抗範圍為20KΩ~100KΩ；除了偵測阻抗外，此電路還可以用來讀取感應電流大的感測器。
　　與顯像系統整合部分，為了讓晶片的類比訊號能讓FPGA開發板所利用，需要類比數位轉換器(Analog to Digital Converter, ADC)來轉換類比訊號，此時以ADC作為主體架構的訊號介面電路，將晶片端與FPGA開發板連接與結合，讓前端讀取到的訊號能在螢幕上顯像出結果。訊號介面電路解析度為12bit，操作速度最高為1.47MHz，類比數位轉換時間為681ns，由於FPGA開發板的VGAOUT只有10bit，故整體解析度為10bit。
　　本讀取電路採用TSMC 0.35um 2P4M 5V製程製作，單一像素布局面積約為30μmX30μm，可讀取電流範圍為0.11pA~164nA；其中BDI模式讀取範圍為3.3pA~164nA，而CTIA模式讀取範圍為0.11pA~14nA，阻抗偵測範圍20KΩ~100KΩ，功率消耗為25.8mW，整體輸出擺幅為1.5V。

關鍵字

陣列式讀取電路 ； 顯像化系統 ； 讀取阻抗 ； 讀取電流 ； 雙模切換

並列摘要

Readout circuit (ROIC) is an important component which connects sensor and interface system. The structure of ROIC interrelates with quality of signal, sensor types, and detecting range, and the key technology is the design of pixel circuit; For implementing ROIC array miniaturization of pixel and the design of sequence output controlling are focus of circuit design.
For multivariate read type and extending read range the pixel circuit divides into current array ROIC and impedance array ROIC. In current array ROIC, the pixel structure consists of coupling Buffer Direct Injection (BDI) and Capacitive Transimpedance Amplifier (CTIA). The impedance of pixel circuit in BDI mode can be reduced by amplifier feedback ti enhance injection efficiency, and it deals with high sensor current. Pixel in CTIA mode dose not require another bias to control input current, and it deals with low sensor current. Both pixel circuit BDI and CTIA have amplifier, and the pixel structure is built of the symmetrical readout circuit in each pixel sharing with middle operational amplifier to micrify pixel size and reduce power consumption. This circuit has four modes to operate with switches. In impedance ROIC array, the pixel structure is a common source circuit which the circuit can detect impedance 20KΩ~100KΩ, and the circuit can not only detect impedance but also read the higher sensed current detector.
In Visualization system, the analog signal of chip must be converted to digital signal that the FPGA develop board is able to process, so it need an Analog to Digital Converter (ADC). By the proxy board uses ADC as the main architecture that the chip can combine with the FPGA, and the signal from detector can image the data on monitor. The proxy board resolution is 12 bits, the system max operation rate is 1.47MHz, ADC conversion is 681ns. Because the DAC inside FPGA is only 10bits, the full system resolution is 10 bits.
This readout chip is designed, simulated, and fabricated by TSMC 0.35μm 2P4M 5V process. The parameter of chip are as follows: the single pixel size is about 30μm x 30μm. read current range is 0.11pA~164nA, BDI mode detects 3.3pA~164nA, CTIA mode detects 0.11pA~14nA, impedance detecting range is 20KΩ~100KΩ, power consumption is 25.8mW, and output swing is 1.5V.

並列關鍵字

array readout circuit ； visualization system ； read impedance ； read current ； dual mode switch

參考文獻

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