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  • 學位論文

以Chipyard為基礎的SoC設計平台FPGA實現之研究

Research on FPGA Implementation of Chipyard-based SoC Design Platform

指導教授 : 黃文吉
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摘要


近年來在軟體上的AI加速器發展越來越多元化,並且在硬體上也有一些的發展及實現,而硬體AI加速器的優勢在於對特定資料格式做運算可以大幅提升速度,僅需使用資料流的方式就可以實現。 本論文針對柏克萊大學提出的硬體開源框架Chipyard,提出一個硬體建構的流程,將RISC-V為基礎的CPU搭配AI硬體加速器整合於FPGA平台,並且完善RISC-V軟體開機流程,讓我們可以通過硬體建構流程調整所需的硬體資源,做出客製化的硬體電路,快速的去對CPU及AI硬體加速器於FPGA開發板上做有效的效能評估。

關鍵字

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並列摘要


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並列關鍵字

FPGA SoC Chipyard

參考文獻


[1] A. Amid, D. Biancolin, A. Gonzalez, D. Grubb, S. Karandikar, H. Liew, A. Magyar, H. Mao, A. Ou, N. Pemberton, P. Rigge, C. Schmidt, J. Wright, J. Zhao, Y. S. Shao, K. Asanović, B. Nikolić, "Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs." in IEEE Micro, 2020, vol. 40, no. 4, pp. 10-21, doi: 10.1109/MM.2020.2996616.
[2] A. Waterman, K. Asanovic, “The RISC-V instruction set manual, volume II: Privileged architecture.” RISC-V Foundation, 2019.
[3] K. Asanović, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitz, S. Karandikar, B. Keller, D. Kim, J. Koenig, Y. Lee, E. Love, M. Maas, A. Magyar, H. Mao, M. Moreto, A. Ou, D. A. Patterson, B. Richards, C. Schmidt, S. Twigg, H. Vo, A. Waterman, "The rocket chip generator." EECS Department, University of California, Berkeley, 2016, Tech. Rep. UCB/EECS-2016-17 4.
[4] C. Celio, P. -F. Chiu, K. Asanović, B. Nikolić and D. Patterson, "BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS," in IEEE Micro, 2019, vol. 39, no. 2, pp. 52-60, doi: 10.1109/MM.2019.2897782.
[5] F. Zaruba, L. Benini. “The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(11), 2629-2640.

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