- 學位論文
6-Gbit/s序列先進科技鏈接展頻時脈產生器
A 6-Gbit/s SATA Spread-Spectrum Clock Generator
摘要
本論文描述一個利用洋蔥波形調變方式，有別於傳統三角波調變方式來實現展頻時脈產生器，可以有效壓低頻譜兩側凸起。所謂展頻技術其基本想法是對時脈信號的頻率做微量的調變，使輸出信號的能量盡量平均分散到可控制的小範圍內，降低各諧波在頻譜上相對應的能量峰值。由於每一個諧波的峰值都會受到衰減，因此可有效的降低整個系統所產生的電磁雜訊干擾。其中在架構上實現了相位頻率偵測器、充放電幫浦、電壓控制振、洋蔥波形調變產生器和除頻器除數上調變，其中展頻百分比等於展頻調變頻率除上輸出頻率，展頻的量為向下展頻4427ppm。電路設計與佈局採用TSMC 0.18um 1P6M CMOS製程，洋蔥波形展頻時脈產生器與洋蔥波形控制電路的晶片佈局總面積包含濾波器為0.25×0.25mm2。其中消耗的功率在6-GHz下為35mW左右。其中心頻率頻譜上的峰值可以被降低19dB左右。
並列摘要
In this work, a spread-spectrum clock generator (SSCG) with onion shaped modulation is presented. It could reduce large peaks that occur at the edges of the spectrum. The SSCG can be applied to most of microprocessor system. It has the effect of spreading the energy of a discrete frequency harmonics over a wider bandwidth, and hence reducing the amplitudes of the harmonics The digitally programmable schemes are implemented in the charge pump , the voltage controlled oscillator , the low-pass filter, the divider and the onion shaped modulator. The spread ratios % equal to spread modulation divides output frequency. With down spreading the spread ratio is 4427ppm. A test fabricated in a 0.18-μm CMOS single-poly six-metal process fabricated. The core area is 0.25×0.25mm2 including the loop filter. It consumes 35mW of power at 6-GHz. Attenuation as high as 19dB is presented. Using an experimental setup, an actual SSCG integrated circuit and theoretically computed results.