- 學位論文
具負電容之多晶矽奈米線鐵電場效電晶體
Poly Silicon Nanowire FeFETs with Negative Capacitance
摘要
近幾年來，元件隨著莫爾定律的微縮，單位面積的功率問題也愈演愈烈。除此之外，物聯網的概念使得降低元件功率勢在必行。為了解決元件功耗日益上升的問題以及實現物聯網的概念，學術界正在研究一種新穎材料——具類似負電容特性的鐵電材料。負電容的概念首先是在2008年被Salahuddin教授提出，是因為鐵電材料內非中心對稱的電偶極結構，使材料本身就帶有偶極距，在電偶極轉換的瞬間產生類似負電容現象，進一步地降低操作電壓與漏電流以滿足目前產業上低功耗元件的訴求。然而，傳統鐵電材料必須在極為嚴苛的條件底下才會生成非中心對稱的結構。本篇論文中，我們利用氧化鉿鋯當種晶層，使得上層的鐵電材料——氧化鉿鋯有較好的結晶性。在材料分析裡，我們成功地利用氧化鋯種晶層使得氧化鉿鋯形成非中心對稱的極化結構，進而在電性表現上有更出色的負電容現象。而我們也將此一鐵電層結構製作再多晶矽奈米電晶體的閘極結構形成鐵電場效電晶體，並且聲稱元件有低於波茲曼熱限制的次臨界擺幅 (60mV/decade)、遲滯現象、負微分電阻。此外，由先前實驗顯示利用快速升溫退火可以使得晶粒大小增大降低晶粒邊界缺陷所造成的影響，除了可提升元件導通電流外還可以進一步改善次臨界特性。利用負電容於快速升溫退火的多晶矽奈米線場效電晶體使元件達到較好的閘極控制能力、次臨界特性、較低的漏電流、以及較高的開關比，已達成高效能及低功耗元件訴求。
並列摘要
For many decades, devices keep scaling by Moore’s law and the power density problem also emerge. On the other hand, the concept of internet of things (IoTs) forces semiconductor industry pay more attention on this problem. In order to realize IoTs, we need to deal with increasing power density. In academic field, there is an interesting material—ferroelectric material, which can exhibit negative capacitance (NC) phenomenon. The concept of NC phenomenon is proposed by professor Salahuddin in 2008. There are intrinsic dipoles existing in this material due to its non-centrosymmetric structure. At the moment of dipoles switching, this NC-like effect can make the gate voltage gain increase and then prompt the devices switch quickly. Devices can operate in lower operation voltage, less leakage current and further achieves the requirement of low-power. However, conventional ferroelectric material, such as PZT, BTO, or BFO are hard to generate non-centrosymmetric structure in thin film. In this thesis, a ZrO2 seed layer was utilized for better crystallization of ferroelectric material—HfxZr1-xO2. From the material analysis, it indicated that ZrO2 seed layer made HfxZr1-xO2 form non-centrosymmetric dipole structure. Ferroelectric material—HfxZr1-xO2 with ZrO2 seed layer was then fabricated on poly silicon nanowire transistor (FeFETs) for low power devices. Moreover, we perform rapid thermal annealing (RTA) process to obtain larger grain size after solid phase crystallization (SPC). In our previous experiment, we know that larger grain size can reduce the side effect caused by defects and further improve performance of devices such as on-state current and sub-threshold swing (S.S.) characteristics. Poly-silicon nanowire ferroelectric transistor (FeFETs) has great gate controllability, S.S. characteristics, low leakage current, and significant on-off ratio. It exhibits great potential for low-power device in the future.