- 學位論文
一個操作於2.4GHz的無參考訊號源之無線1Mbps QPSK解調器
A 2.4 GHz Crystal-less Single-Chip Wireless Receiver for 1Mbps QPSK Demodulation
摘要
本論文以QPSK(Quaternary Phase Shift Keying)數位調變技術實現的鎖相資料解調變電路，其架構基於單一鎖相迴路，藉由追蹤發射端的射頻頻率產生參考訊號，與直接資料解調，同時不需外接石英晶體振盪器，做為參考訊號源，改善傳統架構無線通訊系統傳送端與接收端本地振盪頻率誤差的問題，適用短距離無線通訊系統。整合了相頻偵測器(PFD)、充電汞(Charge Pump)、迴路濾波器(Loop Filter)、壓控振盪器(VCO)、除頻器(Divider)，低雜訊放大器(LNA)，混波器(Mixer)，後級放大器(Post Amplifier)，頻率檢知器 (Frequency Discriminator)與解調變電路(Demodulation)於單一晶片中，達到低功率，低成本與高度整合的目的。 本論文的晶片是使用台灣積體電路公司的0.18μm互補金氧半導體的製程製作，工作於2.4GHz頻段支援短距離傳輸通訊系統，功率消耗小於20mW，接收數位調變訊號QPSK，靈敏度約為-70dBm，位元錯誤率10-3，資料率為1Mbps，相位雜訊在距離載波頻率1MHz時小於-110dBc/Hz。
並列摘要
This paper focusing on QPSK(Quaternary Phase Shift Keying) data demodulator utilizing phase locking technique. The architecture is based on phase locked loop which extracts timing information directly from received RF signal and further demodulates the received data pattern. In other words, it works without reference crystal oscillator and the problem of local oscillator frequency in alignment between transmitter and receiver ends could readily be solved with this new architecture. The main application of this work is for short range wireless communication system. This chip includes PFD, Charge Pump, Loop Filter, VCO, Divider, LNA, Mixer, Post Amplifier, Frequency Discriminator, and Demodulator and several other digital blocks. This is a chip of high integration level and low power consumption. This chip is fabricated in TSMC 0.18μm CMOS technology. It operates at a rate of 2.4GHz and it is well suited for short range data processing. The measured power consumption is below 20mW, the sensitivity for receiving 1Mbps digital modulated QPSK signal is -70dBm with a BER no larger than 10-3. Also the measured phase noise is well below -110dBc/Hz at an frequency offset of 1MHz.