提升積體電路栓鎖防疫能力之設計方法與實現

DESIGN AND IMPLEMENTATION TO IMPROVE LATCHUP IMMUNITY OF CMOS INTEGRATED CIRCUITS

蔡惠雯(Hui-Wen Tsai)

指導教授 ： 柯明道

國立交通大學/電機學院/電子工程系所/博士(2015年)

https://doi.org/10.6842/NCTU.2015.00197

摘要

無資料

關鍵字

栓鎖 ； 防護環 ； 過度電性應力 ； 靜電防護元件

並列摘要

無資料

並列關鍵字

latchup ； guard ring ； EOS ； ESD device

參考文獻

[1] S. Voldman, Latchup. John Wiley & Sons, 2007.

[3] M.-D. Ker and W.-Y. Lo, “Methodology on extracting compact layout rules for latch-up prevention in deep-submicron bulk CMOS technology,” IEEE Trans. Semiconduct. Manufact., vol. 16, no.2, p.319, May 2003.

[5] D. B. Estreich, A. Ochoa, and R.W. Dutton, “An analysis of latch-up prevention in CMOS IC.s using an epitaxial-buried layers process,” in IEDM Tech. Dig., 1978 pp. 230–234.

[6] A. G. Lewis, R.A. Martin, T.-Y. Huang, et al. “Latchup performance of retrograde and conventional n-well CMOS technologies,” IEEE Trans. Electron Devices, vol. 34, no. 10, pp. 2156-2164, Oct. 1987.

[8] S. Voldman, E. Gebreselasie, L. Lanzerotti, T. Larsen, N. Feilchenfeld, S. St. Onge, A. Joseph, and J. Dunn, “The influence of a silicon dioxide-filled trench isolation structure and implanted sub-collector on latchup robustness,” in Proc. IRPS, 2005, pp.112-120.