光阻烘烤製程的不均勻性對CD之影響

隨著電腦科技的進步,記憶體晶片的容量需求越來越大,像動態隨機存取記憶體(dynamic random access memory, DRAM)以及快閃唯讀記憶體(flash read-only memory, flash-ROM)等晶片,積體電路(IC)製造者勢必想用最小的晶圓面積作出最大的記憶容量,因此必需不斷的減小元件特徵尺寸來持續的降低成本。而提高IC電路製程光微影(lithography)解析度的方法有很多,但是最有效的方法卻只有不停的縮短波長,而使用的波長越短光源能量就越弱,若直接加長曝光時間雖也能有足夠能量傳給光阻進行光反應,但是這樣作會嚴重損失產能及曝光穩定性。所以現階段較可行的方式是利用化學放大型光阻(chemically amplified photoresist, CAPR)製程,另將光阻獲得能量的方式,分成曝光及烘烤兩個部份。因為烘烤關係到CAPR H+連續催化反應的能量,所以對關鍵尺寸(critical dimension, CD)的影響和曝光一樣的重要,此外,烘烤步驟中光阻的溫度均勻性因為矽晶圓與烘烤硬體之接觸問題,接觸熱傳導的均勻性無法能夠像光一樣的精準正確,因此曝光前烘烤(pre bake, PB)及曝光後烘烤(post exposure bake, PEB)的接觸問題,會直接影響CAPR內部光化學反應的均勻性，而會造成晶圓半邊的CD異常及一半的良率損失現象。為了探討光阻烘烤製程的不均勻性對CD之影響,我們利用wafer與烤盤接觸瞬間,熱由高溫傳導至低溫,使的plate的溫度下降了ΔT,因為下降的程度與wafer和plate接觸面積大小有關,因此可利用此參數ΔT方便我們來判斷Wafer烘烤製程之狀況。一般而言PEB的主要功能是提供CAPR內部H+連續催化反應的能量,影響CD應該是最直接且最重要的,但是實驗結果,發現不論是248 nm或193 nm 的PB影響都大於PEB,因此PB比PEB更為重要。並且發現 PB 與 PEB 對CD的影響方向相反,例如當DUV photoresist 在wafer與plate之間有一0.5 mm 的間隙Tilt,而且相同的條件下, PB使線距增加94~340Å,而PEB卻使線距減少61~109Å。然而I-Line雖然對線寬有些微影響,但因為規格較寬鬆,因此可不考慮CD的變化。我們也利用ANSYS軟體建立了一個簡化的三維有限元素模型。此模型預測的晶片表面溫度與實際T-Map儀器所量測的數據差異小於±2℃。預測的wafer與plate接觸瞬間plate內部溫度下降ΔT與實際plate溫度下降ΔT的數據差異小於±0.2℃。而且此模型針對各種不同的tilt試片所預測的CD與溫度測試實驗有著極佳的相關性。最後我們發現了足於代表光阻的PB/PEB烘烤製程狀況的plate溫度下降參數ΔT,並且驗證了ΔT與CD的直接關聯性,可利用此模型來協助預測新產品或新製程條件能忍受的範圍。

關鍵字

光阻；線寬

並列摘要

The advancement of the computer science and technology has resulted in an increasing demand for memory chips such as dynamic random access memory (DRAM) and flash read-only memory (Flash-ROM) chips, etc. Manufacturers aim to develop chips that have maximum possible memory capacity with minimum chip area while simultaneously reducing the cost. With reference to Moore’s law, many methods can be used to improve IC circuit image resolution; however, the most effective method is to use the increasingly shorter wavelengths, which require weaker light source. By extending exposure time will allow sufficient energy to pass through photoresist, thus enabling the photoacid reaction to proceed; however, this will result in heavy losses, which can produce and expose stability. Hence a more feasible solution by the usage of chemically amplified photoresist (CAPR) process is created. The CAPR process has been said to obtain the energy of the photoresist and can be divided into exposed and baked components. Bake heat-conduction by wafer and hot plate contact control uniformity is unlike light, which is perfect and correct. In addition, contact issues on pre-bake (PB), post-exposure bake (PEB) and direct influence uniformity of the photochemical reaction within CAPR can usually cause yield loss on half of the wafer. Method to guarantee the performance baked by CAPR is an extremely important subject in the semi-conductor manufacturing at the moment. Generally speaking, the main function of PEB is to support the energy of CAPR H+ continuous catalysis, which is the most direct and important influence on critical dimension (CD). The experimental result has found that regardless of the PB of 248 nm or 193 nm, PB influence is still greater than PEB, thus PB has proven to be more important than PEB. The finding of PB contrary to the direction of PEB impact on CD will also be conducted. For example, if DUV photoresist wafer is 0.5 mm on both PB and PEB plate gap, PB will increase line distance by 94~340Å while PEB will reduce line distance by 61~109Å. Although I-line has little influence on some CDs, the relatively loose specification will not consider the change in CD. We will utilize software to set up a simple and limited element model in three-dimension. The wafer surface temperature predicted by the model and actual T-Map instrument data difference examined by quantity is less than ±2℃. Wafer and instantaneous plate-plate contact temperature drop ΔT, actual plate temperature drop ΔT and ΔT data difference are predicted to reach below ±0.2℃. Impacts will be seen in CD temperature, 248 nm photoresist at PB 0.34 nm/℃, PEB –0.21 nm/℃ in addition to 193 nm photoresist at PB 1.23 nm/℃ and PEB –0.39 nm/℃. The model used to predict CD wafer and temperature to all gaps of contact experiment has proved to possess extreme reliability. In conclusion, PB/PEB was found capable in representing ongoing photoresist bake plate, which uses drop temperature ΔT parameter in addition to the direct relationship with the one with verified ΔT and CD. This model can be used to assist in the prediction of the standing range for new products or new process conditions.

並列關鍵字

photoresist ； critical dimension

參考文獻

[3] Paul D. Friedberg, Cherry Tang, Bhanwar Singh, Thomas Brueckner, Wolfram Gr dke, Bern Schulz, Costas J. Spanos, Time-based PEB adjustment for optimizing CD distributions, (2005).

[5] Bryan Rice, Heidi Cao, Jeanette Roberts, Manish Chandhok Intel Corporation, Effects of Processing Parameters on Line Edge Roughness (LER), 2 (2002).

[6] Donald A. Neamen, Semiconductor Physics & Devices, (2003).

[8] Wen-Li Wu, Jim Leu, "Small angle x-ray scattering measurements of lithographic patterns with sidewall roughness from vertical standing waves", American Institute of Physics, 1 (2007).

[9] International Technology Working Group (ITWG), "Lithography", International Technology Roadmap for Semiconductors 2007 edition, 20 (2007).

國際替代計量

光阻烘烤製程的不均勻性對CD之影響

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