在追求元件尺寸微縮的競爭道路上,除了要降低短通道效應外,如何繼續提升元件密度及降低功耗也是大家關注的議題,因此,各式多閘極的新型元件陸續被提出。為了精準的預測多閘極元件的次臨限擺幅(Subthreshold swing, SS)及汲極偏壓導致通道能障降低效應(Drain-induced barrier lowering, DIBL),我們使用電腦輔助設計軟體(TCAD)並透過量測實驗數據校正建立結構,來模擬業界的高介電常數金屬閘極之塊狀基板鰭式場效電晶體(HKMG bulk FinFET )。此外,我們引入自然常數及修正係數,藉由物理的模型推導,建立SS及DIBL的經驗公式,如此便可以透過TCAD模擬達到預測多閘極元件最佳化的情形。
In order to keep pace with the Moore’s Law, suppressing short-channel effects through novel multiple gate geometry architectures of device is a practical solution to make shrinking possible. To accurately predict the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) of multi-gate FETs, we employ a commercial TCAD code on the industrial bulk FinFETs. The TCAD calibration task is well done via a natural length and its experimentally determined correction coefficient. This predictive TCAD enables the optimization of multi-gate FETs with suppressed SS and DIBL.