用於系統晶片中單埠與多埠記憶體之自我修復技術

Built-In Self-Repair Schemes for Single-Port and Multiple-Port Memories in SOCs

許智強(Chih-Chiang Hsu)

指導教授 ： 李進福

國立中央大學/資訊電機學院/電機工程學系/碩士(2005年)

摘要

在系統晶片(SOCs)中，內嵌式記憶體(embedded memories)是最常使用到的核心電路，並且它佔據了晶片大部分的面積。因此，內嵌式記憶體(embedded memories)的良率通常也主宰著系統晶片(SOCs)的良率。自我修復(built-in self-repair)技術是針對改善內嵌式記憶體良率的有效方法之ㄧ。本篇論文針對在系統晶片中單埠和多埠記憶體分別提出了兩種方法。在單埠記憶體的自我修復方法中，我們提出了一個名為錯誤範圍比對冗餘分析(faulty-range-comparison redundancy-analysis)方法，而此種方法能支援兩種冗餘組態:一為備份列/備份行(spare row/spare column)另一為備份列/備份IO(spare row/spare IO)。實驗數據顯示一個針對單個(四個)8k 64-bit的單埠記憶體的自我修復電路所占整個記憶體面積為3.38%(0.84%)。 再者，冗餘分析的修復率是接近最佳化演算法的修復率。在多埠記憶體的自我修復方法中，我們設計一個診斷(diagnosis)演算法來定位埠之間的錯誤(inter-port faults); 以避免因錯失實際錯誤位置而導致的良率降低的效應。而且，我們將原本針對單埠記憶體的冗餘分析方法稍加修改，以符合多埠記憶體的需求。實驗數據顯示一個針對單個(四個)8k 64-bit的多埠記憶體的自我修復電路所占整個記憶體面積為3.2%(1%)。最後，我們提出的自我修復電路架構能支援系統晶片中多個記憶體的修復。

關鍵字

自我修復 ； 記憶體

並列摘要

Embedded memories are most used cores in system-on-chips (SOCs) and usually represent a significant portion of the chip area. Therefore, the yield of embedded memories usually dominates the yield of SOCs. Built-in self-repair (BISR) technique is one useful methodology for improving the yield of embedded memories. This thesis presents two BISR schemes for single-port and multiple-port memories in SOCs. In the BISR scheme for single-port memories, a faulty-range-comparison redundancy-analysis (FRCA) algorithm is proposed to allocate two types of redundancy organization (spare row/spare column and spare row/spare IO). Experimental results show that the area overhead of the BISR scheme for one (four) 8k 64-bit single-port memories is 3.38% (0.84%), where each memory with two spare rows and four spare columns is assumed. Also, the repair rate of FRCA is close to the repair rate of the exhaustive algorithm. In the BISR scheme for multiple-port memories, a diagnosis algorithm is proposed to locate the inter-port faults; this can avoid the yield reduction caused by inter-port faults in multiple-port memories. Also, a modified FRCA is used to allocate spare elements. Experimental results show that the area overhead of the BISR scheme for one (four) 8k 64-bit two-port memories with two spare rows and four spare columns is 3.2% (1%). Both BISR schemes can support the repair of multiple memory instances in SOCs.

並列關鍵字

BIST ； BISR ； self repair ； memory ； BIRA ； redundancy analysis

參考文獻

[1] R.-F. Huang, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, and Y.-J. Chang, “Fail Pattern Identification for Memory Built-In Self-Repair”, in Proc. 13th Asian Test Symposium. Nov. 2004, pp. 366-371.

[2] F. Karimi and F. Lombardi, “Parallel Testing of Multi-Port Static Random Access Memories for BIST”, in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, Oct. 2001, pp.271-279.

[3] S. Hamdioui and A. J. van de Goor, “Efficient Tests for Realistic Faults in Dual-Port SRAMs”, IEEE Trans. on Computers, vol. 51, no. 5, May 2002, pp. 460-473.

[4] S. Hamdioui, A. J. van de Goor, D. Eastwick, and M. Rodgers, “Realistic Fault Models and Test Procedure for Multi-Port SRAMs”, in Proc. IEEE Int. Workshop, Memory Technology, Design, and Testing, Aug. 2001, pp.65-72.

[5] S. Hamdioui and A. J. van de Goor, “Efficient Tests for Realistic Faults in Dual-Port SRAMs”, IEEE Trans. on Computers, vol. 51, no. 5, May. 2002, pp. 460-473.