數位電路傳輸品質之統計評量

Statistical Evaluation of Transmission Quality for Digital Logic Circuits

龔彥中(Yen-Chung Kung)

Advisor ： 陳竹一

國立中央大學/資訊電機學院/電機工程學系/碩士(2007年)

Abstracts

隨著數位電路工作頻率的提升，信號受到時序抖動以及時脈偏移的影響也越來越劇烈。本篇論文將以正反器串做為模型，並且利用統計分析的方法，來分析數位電路傳輸時受到時序抖動以及時脈偏移影響時的傳輸品質。應用分析的結果找到最佳的時序設定，供設計者參考以提昇電路工作的可靠性。

Keywords

數位電路 ； 傳輸品質

Parallel abstracts

As the frequency of digital logic circuit rises up, the influence of jitter and skew on the signal is getting more serious. In this thesis we build a model based on a D flip-flop chain and use a statistical method to evaluate the transmission quality of digital logic circuit affected by jitter and skew. The best timing setting can be determined and provided to designers to improve the circuit reliability via this evaluation.

Parallel keywords

transmission quality ； digital logic circuits

References

[1] Harold Larson, “Introduction to Probability”, Addison-Wesley, 1995

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[5] Jie Sun, Mike Li, Jan Wilstrup, “A Demonstration of Deterministic Jitter (DJ) Deconvolution”, IEEE Instrumentation and Measurement Technology Conference, 2002, vol. 1, pp. 293-298

[8] Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Kucukcakar, Eby Friedman, “Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times”, International Symposium on Quality Electronic Design, 2006

[10] Mike Li, Jan Wilstrup, “On the Accuracy of Jitter Separation from Bit Error Rate Function”, International Test Conference, 2002, pp. 710-716