混合式加法器設計

Hybrid Adder Designs

張劭鍇(Shao-kai Chang)

指導教授 ： 魏慶隆 ； 謝韶徽

國立中央大學/資訊電機學院/電機工程學系/碩士(2010年)

摘要

本論文提出一個快速的六十四位元加法器﹐使用動態的邏輯電路及傳輸閘的架構﹐應用於Brent-Kung Tree。此加法器為混合式的加法器架構，其採用前瞻進位單元和多工器且具有8個邏輯閘階層。由模擬結果顯示，混合加法器在最壞情況的延遲為298ps，而使用的製程技術為TSMC 0.18 um 2P6M CMOS technology，電源電壓為1.8伏特。同時我們也在其他的先進製程中模擬，模擬結果顯示，混合加法器在最壞情況的延遲為110ps，而使用的製程技術為UMC 90 nm 1P9M CMOS Low-K technology，電源電壓為1伏特。

關鍵字

混合式加法器 ； 前瞻進位加法器 ； 跳躍進位加法器 ； 平行預算加法器

並列摘要

The thesis presents a fast 64-bit adder based on domino logics and pass transmission gates in the Brent-Kung Tree. The proposed adder uses a hybrid adder of Carry Look-Ahead and MUX architecture in 8 logic levels. Simulation results show that the proposed hybrid adder achieves a delay of 298ps, where the TSMC 0.18 um 2P6M CMOS technology with the supply voltage of 1.8V. Based on UMC 90 nm 1P9M CMOS Low-K technology with the supply voltage of 1V, the proposed 64-bit hybrid adder achieves a delay of 110ps with 6mW power dissipation.

並列關鍵字

Parallel Prefix adder ； Carry Skip Adder ； Carry lookahead adder ； Hybrid Adder

參考文獻

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