在此論文中 ,我們針對快閃記憶體中平面化技術提出討論,並重建 Greedy 垃圾收集方法及靜態平面化演算法作為與本論文所提出之高效能且低複雜度之平面化設計技術(循序垃圾收集技術,SGC)的比較對象,用來延長快閃記憶體的壽命及平衡其使用率。 論文中包含目前現有的快閃記憶體的種類及優缺點,並介紹快閃記憶體中需要哪些重要元件來維持讀寫速度及壽命。此外會介紹目前現有的平面化技術有哪些類別,以及為什麼需要平面化技術,針對現有的各種平面化技術的優缺點來做分析,並討論對於現在的快閃記憶體這些技術是否適用。 本論文所提出之平面化技術稱為循序垃圾收集技術(SGC) ,所提出的循序垃圾收集技術(SGC)比起現有的設計平面化能更加平均化且有較低的設計複雜度,因此快閃記憶體的壽命可以隨之有效的延長;此外本論文提出之循序垃圾收集技術不需要額外調整觸發平面化技術的門檻。本論文所提出的循序垃圾收集技術可以輕易地使用軟體的方式去實現或是使用硬體的方式去實現。 論文中將比較Greedy 垃圾收集方法及靜態平面化演算法及循序垃圾收集技術這些種方法,並針對抹除次數中的最大值,標準差,平均抹除次數,以及抹除時的額外開銷這些數據來比較。 最後為了證明循序垃圾收集技術是可以輕易地在軟體及硬體環境上實現,使用FPGA開發板來驗證方法是否可以在硬體上實現。
In this thesis, we discuss the techniques of wear leveling in the flash memory system and also rebuild algorithm of Greedy garbage collection and static wear leveling for comparison. Thus a low-complexity high-performance wear leveling is proposed and it can extend lifetime of the flash memory and balance the utilization of each block. This thesis analyzes the advantages and disadvantages in current wear leveling techniques. Besides, we introduce the important issues to maintain read/program performance and the lifetime in the flash memory. In addition, we will introduce the current wear leveling methods, and discuss the complexity of these approaches. The proposed wear leveling algorithm is called sequential garbage collection (SGC), SGC outperforms existing designs in terms of wear evenness and low design complexity. The lifetime of the entire flash memory can be greatly lengthened by the proposed SGC. In addition, the proposed SGC doesn’t require any tuning threshold parameter. The low-complexity low-cost SGC makes it easy to be implemented by firmware-based or hardware-based approaches. This thesis compares Greedy garbage collection, static wear leveling and sequential garbage collection (SGC) in terms of maximum block erase count, the standard deviation of the block erase count, average erase count and overhead of wear leveling. Finally, to prove the sequential garbage collection (SGC) is easy to be implemented by firmware-based or hardware-based approaches. We use the FPGA board to implement the propose algorithm and verify the performance of the proposed algorithm.