利用改良式迴路濾波器與有效率係數合成於高階連續時間三角積分調變器之穩定性改善

Improved Stability of High-Order Continuous-Time Sigma-Delta Modulators with Modified Loop Filters and Efficient Synthesis

鄭富元(Fu-Yuan Cheng)

指導教授 ： 蔡宗亨

國立中正大學/工學院/電機工程學系/碩士(2015年)

摘要

連續時間三角積分器在寬頻帶的應用上有著相當的優勢，隨著階數增加可以讓雜訊移頻效果越明顯，在低超取樣率下達到高解析度。但是階數高也會使系統的穩定性下降，嚴重時將會破壞系統效能，尤其是連續時間三角積分調變器還有著額外迴路延遲的重要問題。CT的額外延遲包括DAC回授路徑的ELD與迴路濾波器內類比積分路徑的延遲。
本論文將以連續時間三角積分調變器為主軸來研究改善穩定性問題。首先在係數上提出有效率的直接S-domain係數合成及補償運算，可直接以CT的Chebyshev type II轉移函數求出CT迴路濾波器上S-domain的係數和ELD補償，非常直觀的設計方式且快速又精確。基於Root Locus與S-plane上極點移動的係數修正方法來增強穩定性與動態範圍。在架構上針對高階迴路濾波器內類比積分路徑的額外延遲問題，提出四階的改良式推疊架構來減少CT積分器的額外延遲影響。對於DAC回授路徑的額外迴路延遲補償則使用迴路濾波器內部的微分路徑完成，並且對於在諧振器(Resonator)架構上微分路徑的ELD補償係數衰減的缺點做係數零點補償。本論文實現一個頻寬10MHz的CT Sigma-Delta ADC，包含四階Active-RC積分器和4位元量化器，取樣頻率為280MHz，使用TSMC 0.18um製程來實現，SNDR為83.635dB。

關鍵字

穩定性 ； 類比數位轉換器 ； 連續時間三角積分調變器 ； 額外迴路延遲 ； 有效率係數合成

並列摘要

The continues-time sigma-delta convertor has advantages on wideband applications. Noise shaping can be obviously observed by increasing the order and obtained a high resolution with a low oversampling rate. On the other hand, higher order systems suffer from stability problems and the system performance may compromised especially that the continues-time sigma-delta modulator has to consider the excess loop delay.
The thesis presented a continuous-time delta-sigma modulator with 10MHz bandwidth. The structure of continuous-time delta-sigma modulator included 4th order active rc integrator and 4bits quantizer. This thesis improves the stability of the continuous-time sigma-delta modulator. First of all, the coefficients are efficiency synthesized and compensated in the S domain based on the out of band gain and root locus modification. The stability and the dynamic range are improved.
To compensate the excess delay on the analog integrator in the loop filter, the modified stack structure is proposed. The internal differential path in the loop filter is utilized for the excess loop delay compensation for the DAC. The coefficient zero compensate is employed to fulfill the ELD compensating coefficients degraded on the differential path of the resonator. The sampling rate is 280MHz and the SNDR is 83.635dB. The chip is fabricated in TSMC 0.18um process.

並列關鍵字

Stability ； analog-to-digital converter ； continues-time sigma-delta modulator ； excess loop delay ； efficient synthesis

參考文獻

[2] T. C. Carusone, D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 2011.

[6] J. A. Cherry and W. M. Snelgrove, “Excess loop delay in continuous-time delta-sigma modulators,” IEEE Trans Circuits Syst. II, Analog Digit. Signal Processing, Vol. 46, no. 4, April 1999.

[7] M. Ortmanns, F. Gerfers, and Y. Manoli, "A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma Delta Modulator," IEEE Transaction Circuits and Systems-I, vol.52, no. 8, pp. 1515 -1525, Aug. 2005.

[8] H. Shamsi, O. Shoaei, “A novel structure for the design of 2-1-1cascaded continuous time delta sigma modulators,” IEEE ISCAS, pp. 4751-4754, May2006.

[9] R. Tortosa, J.M. de la Rosa, A. Rodriguez-Vazquez, F.V. Fernandez, “A direct synthesis method of cascaded continuous-time sigma-delta modulators,” IEEE ISCAS, vol. 6, pp. 5585 – 5588, May 2005.