- 學位論文
應用於H.264/AVC和H.265/HEVC之高效率視訊編碼方法和DSP實現
Efficient video coding methods and DSP realization for H.264/AVC and H.265/HEVC standards
摘要
近年來隨著通訊和面板技術的迅速發展，全高畫質(FHD)和超高畫質(UHD)解析度多媒體視訊應用，愈來愈受歡迎。目前主流視訊標準H.264/AVC和新一代視訊標準H.265/HEVC也因應而生。然而，為了能達到高壓縮率的目標，H.264/AVC和H.265/HEVC編碼的過程相當耗時，這主要因編碼為系統內的框內/框間預測(intra/inter prediction)和轉換/量化(transform/quantization)等模組，均具有非常高的計算複雜度，導致無法達到即時的視訊傳輸。為了降低H.264/AVC和H.265/HEVC編碼複雜度，本論文分別提出快速框內預測模組、提早終止轉換/量化模組和高效率位元率控制模組等有效視訊編碼演算法，並進一步完成DSP的硬體實現。 為了改善H.264/AVC視訊編碼效能，論文首先針對框內預測模組提出快速模式決策(fast mode decision)演算法，我們利用區塊間關聯性(inter block correlation)來有效減少框內預測模式的數量，實驗結果證明在犧牲很小的視訊品質下，編碼速度可加速2~5倍。其次，由於框內/框間預測模組中的整數離散餘弦轉換(DCT)和量化(Q)佔有相當高的運算量，為了減少DCT/Q運算複雜度，我們提出一結合連續消除演算法(SEA)和Parseval定理之高效率全零區塊(AZB)偵測演算法，由模擬結果可發現，論文所提演算法比其他快速AZB偵測方法可再減少約12%~22%的運算量。最後，當在視訊傳輸時，為了保持H.264/AVC在接收端有穩定的視訊品質，我們建構一改良型H.264/AVC位元率控制系統，利用已編碼區塊檔頭位元的平均值來預測待編碼區塊的檔頭位元，進而決定位元率配置(rate allocate)和決定量化參數(QP)，並同時利用時空關聯性(spatial-temporal correlation)做MAD線性預測，從實驗結果可發現，我們所提出的改良型位元率控制系統，除可避免H.264/AVC 傳輸初期畫面遺失的不連續感，並且也提升了整體傳輸視訊的品質。 此外，本論文也針對H.265/HEVC標準提出一有效的視訊編碼演算法，為了降低H.265/HEVC編碼的運算複雜度，加速轉換模組(TU)之提早決策演算法(ETDA)是重要方法之一，其中藉由判斷差值四分樹(RQT)中非零DCT係數量(NNZ)之EDTA演算法(NNZ-ETDA)是現今最新的方法。為了進一步改良NNZ-ETDA的效能，我們利用視訊的高時空關聯性，提出一個適應性RQT深度之NNZ-ETDA演算法(ARD-NNZ-ETDA)來加速TU的編碼時間，由實驗結果可以發現，論文所提ARD-NNZ-ETDA和HEVC (HM8.1)的時間改善率(TIR)平均約61.26%~81.48%，當與NNZ-ETDA比較時，TIR則可再增加平均約8.29%~17.92%。 最後論文將所提出H.264/AVC和H.265/HEVC高效率的視訊編碼方法，利用多媒體數位訊號處理(DSP)器進行硬體實現，我們利用ADI所發行ADSP-BF548 的開發板來進行測試。為了能有效將所提H.264/AVC和H.265/HEVC系統直接嵌入ADSP-BF548，我們提出一高效率記憶體配置(HEMA)演算法，來改善ADSP-BF548記憶體配置的效能。HEMA首先統計H.264/AVC和H.265/HEVC系統內各個模組的運算複雜度，再將高運算量的模組從運算速度較慢的外部記憶體(L3)，有效的重新配置在運算速度較快的內部記憶體(L1、L2)來改善編解碼效率。最後，透過直接記憶體存取(DMA)功能、記憶體的最佳配置和平行運算來進行硬體加速，進一步實現即時解碼的硬體實現。從實驗結果驗證，論文所提H.264/AVC和H.265/HEVC系統的視訊播放可達30 fps以上，適合應用在現今的消費性電子產品上。
關鍵字
none並列摘要
With the rapid development of digital multimedia service, full high definition (FHD) and ultrahigh definition (UHD) resolution is more and more popular in the multimedia service. The up-to-date video coding standards including H.264/MPEG-4 Advance Video Coding (AVC) and H.265/MPEG-H High Efficiency Video Coding (HEVC) could support FHD and UHD resolution video applications, respectively. However, H.264/AVC and H.265/HEVC standards require enormously computational complexity in encoding process which results from the time-consuming works of intra/inter prediction and transform/quantization (DCT/Q) modules. Therefore, it will be hard to realize the real-time applications. In order to reduce the computational complexity of H.264/AVC and H.265/HEVC, we propose some efficient video coding methods including fast intra prediction module, early terminated DCT/Q module and efficient rate control module, respectively. In this dissertation, we propose some efficient coding methods for H.264/AVC standard to speed up the encoding process. Firstly, we develop a fast intra mode decision algorithm for H.264/AVC which takes advantage of the mode correlation between MBs/blocks with a suitable threshold according to interblock correlation. The proposed fast decision algorithm can provide a good tradeoff between the R-D performance and the computational complexity. Secondly, a more efficient and fast algorithm is proposed in DCT/Q module using early detecting all zero blocks (AZB) which combines Parseval theorem and successive elimination algorithm (SEA). The simulation results show that the proposed algorithm achieves approximately a 12%~22% computational saving when compared to the existing methods. Finally, in order to finish real-time video streaming scenario, a more efficient rate control scheme is proposed. A fast and best selection of initial QP is first proposed in the GOP layer rate control. Then, an improved MAD prediction model and overhead bits prediction method is adopted in the MB layer rate control. The simulation results show the proposed scheme improves the number of frame skipped and reduces the quality deviations of initial frames by choosing the best initial QP. In addition, we also propose an efficient coding method for H.265/HEVC standard in this dissertation. To reduce the computational burden of H.265/HEVC encoder, an early transform unit (TU) decision algorithm (ETDA) is adopted to prune the residual quadtree (RQT) at early stage based on the number of nonzero DCT coefficients (called NNZ-EDTA). In order to further improve the performance of NNZ-ETDA, we propose an adaptive RQT-depth decision for NNZ-ETDA (ARD-NNZ-ETDA) by exploiting the characteristics of high temporal-spatial correlation. An adaptive depth of RQT is employed to the NNZ-ETDA to further reduce the computational load of TU module. Simulation results show that the proposed method can achieve time improving ratio (TIR) about 61.26%~81.48% when compared to the H.265/HEVC test model 8.1 (HM 8.1) with insignificant loss of image quality. Compared with the existing NNZ-ETDA, the proposed method can further achieve an average TIR about 8.29%~17.92%. The latest generation of digital signal processors (DSPs) can support very flexible codec at a relative low cost. Therefore, in order to further achieve the DSP realization for the proposed efficient H.264/AVC and H.265/HEVC standards, we embed the codec on the ADSP-BF548. To achieve the fast requirement of embedded H.264/AVC and H.265/HEVC based on ADSP-BF548, we propose a highly efficient memory assignment (HEMA) technique to modify the allocated internal memory and optimize the source codes. Firstly, the HEMA analyzes the complexity of encoding modules for H.264/AVC and H.265/HEVC, and then we re-allocate the reference frame from L3 DDR-RAM to L2 SRAM to increase the speed of execution of motion estimation (ME) module and re-allocate the function of consuming module from L3 DDR-RAM to L1 SRAM. Finally, we make use of direct memory access (DMA) and the default function of ADSP-BF548 to carry out program steps. In addition, the parallelism between algorithm execution and data movement has been fully exploited using DMA. Experimental results demonstrate that the decoding rate can reach above 30 fps to acheve real-time applications.