應用空間變換的雙線性內插法的分析與實現

ANALYSIS AND IMPLEMENTATION OF THE SPACE VARYING BILINEAR INTERPOLATION

楊嘉樑(Chia-Liang Yang)

指導教授 ： 蔡明傑

大同大學/電機資訊學院/電機工程學系所/碩士(2007年)

摘要

本論文得以順利完成首先要感謝指導教授 蔡明傑教授在研究上的
啟發及悉心指導與諄諄教誨並在研究期間細心的教導，使得本人在學業
以及待人處事上均受益匪淺，在此深表誠摯的謝意。
在這兩年來研究所的生活裡，非常感謝 黃淑絹導師及所有教過我
的老師在課業上的指導，更感謝黃炳源以及陳建維學長、宋文才、康明
賜、陳昱勳、鄧詠維同學以及每一位在學業或工作上的提供幫忙與協助
的人。
最後要感謝我的家人及同事在各方面給予無限的支持與精神上的關
懷鼓勵，使我能順利完成本論文並與您們共享這份喜悅。

關鍵字

即時 ； PSNR ； 二維雙線性 ； 內插法 ； 灰階分析

並列摘要

This thesis mainly for study the improvement of image quality of video format
conversion based on the space varying bilinear interpolation, and realize the design by FPGA. Conventional bilinear interpolation method has the characteristic of the inverse ratio between sampling grayscale level and the distance. Such method has a serious blurring problem due to the linear structure. We propose the space varying bilinear interpolation with various sharpness constant to get better performance and sharper image than that interpolated by the conventional bilinear interpolation.
Personal computer simulations using read images performance of the proposed
algorithm. The performance evaluation is base on the PSNR and Sharpness between the original and reconstructed image, and the results were shown better than the traditional bilinear interpolation algorithms. Besides, it also reveals that the novel method can process high resolution, with true color picture of size up to 1024*768 pixels at real-time video of 60 frames/sec. The implementation can under less embedded memory requirement.

並列關鍵字

Real-time ； PSNR ； 2-D Bilinear ； FPGA ； Interpolation ； Gradient Analysis

參考文獻

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[3] J. W. Hwang and H. S. Lee, “Adaptive image interpolation based on local gradient features,” IEEE Signal Processing Letters, vol. 11, no. 3, Mar. 2004.

[8] S. C. Hsia,B. D. Liu,J. F. Yang and C. H. Huang, “A parallel video converter for displaying 4:3 image on 16:9 HDTV receivers,” IEEE Trans. on Circuits and Systems for Video Technology, vol. 6, pp. 695-699, Dec. 1996.

[10] S. Ramachandran and S. Srinivasan, “Design and FPGA implementation of a video scalar with on-chip reduced memory utilization,” in proc. of Euromicro Symposium on Digital System Design, vol. 1-6, pp. 206-213, Sept. 2003.

[11] B. G. Lee, Y. M. Kwon, C. G. Oh and Y. Chung, “Design of a scan converter using cubic splines,” IEEE Trans. on Consumer Electronics, vol. 47, pp. 6-9, Feb. 2001.