10位元40MHZ管線式類比數位轉換器

10-BIT 40-MS/S PIPELINE ANALOG TO DIGITAL CONVERTER

黃世興(Shih-Sing Huang)

指導教授 ： 詹耀福

大同大學/電機資訊學院/電機工程學系所/碩士(2008年)

摘要

本論文中利用TSMC 0.18μm 1P6M mixed signal的製程來完成一個10位元管線式類比數位轉換器之設計模擬，其取樣頻率為40MHz，使用的供給電壓為1.8V。本次設計為九級(stage)的管線式類比數位轉換器，前八級採用1.5-bit/per stage的技術，最後一級則為一個2-bit的快閃式類比數位轉換器。整體電路的設計採用全差動的架構來降低雜訊的干擾。 在電路模擬方面，我們利用HSPICE來進行模擬，使用了台積電0.18微米互補式金氧半製程設計，對於10位元40MHz管線式類比數位轉換器的模擬結果如下：在輸入0.5078125MHz的正弦波時，訊號對雜訊比(SNR)為57.8dB，有效位元數(ENOB)為9.32位元，電路的功率消耗為117mW。

關鍵字

類比數位轉換器，管線式

並列摘要

In this thesis, we design a 10-bit 40MSample/s pipelined analog-to-digital converter (ADC) by TSMC 0.18μm 1P6M mixed signal process technology. The supply voltage is 1.8V. The ADC architecture is nine stage pipelined ADC in this design, we adopt 1.5-bit/per stage architecture and a 2-bit flash ADC in the last stage. In order to decrease noise interference, the whole circuit is designed by fully differential structure.
The ADC is simulated by HSPICE using TSMC 0.18μm 1P6M mixed signal process technology. The proposed ADC has the following performances: For 0.5078125MHz sine wave input, the SNR is 57.8dB, the ENOB is 9.32bits, and the power consumption is 117mW at the maximum conversion rate.

並列關鍵字

ADC ； Pipeline

參考文獻

[1] R. Jacob Baker, “ CMOS﹕Mixed-Signal Circuit Design,” John Wiley & Sons, Boston, June 2002.

[6] Chien-Hsueh Chiang, “ High Gain & High Bandwidth Op-Amp For Pipeline ADC,” Master Thesis, National Tsing Hua University, July 2005.

[8] Zong-Xian Lv, “ Design of a Pipelined Analog to Digital Converter for IEEE 802.11a WLAN,” Master Thesis, National Chung Hua University,, July 2004.

[9] D. A. Johns and K. Martin, “ Analog Integrated Circuit Design,” John Wiley & Sons, New York, 1997.

[10] Josh Carnes, Gil-Cho Ahn and Un-Ku Moon, “A 1V 10b 60MS/s Hybrid Opamp-Reset/Switched-RC Pipelined ADC,” IEEE J. Solid-State Circuits, pp. 236-239, Nov. 2007.