- 學位論文
平行及管線結合架構之高階加密標準處理器
PARALLEL AND PIPELINE ARCHITECTURE-COMBINED FOR AES PROCESSER
摘要
很多通過網絡傳輸的數據都是以純文件形式發送的，這些數據很容易被其他人獲取，導致一些敏感信息外泄。為了保證這些信息的安全，加密起了關鍵的作用，AES演算法的過程是把這些信息翻譯成密碼形式，且附加了一個密鑰或一個密碼，這樣就保護數據免於入侵者的入侵，最初大部分的AES演算法是用軟體來實現，不過軟體的加解密已跟不上傳輸的速度，這就導致了AES由硬體實現。 大致上硬體架構分為平行處理及管線處理，平行處理適合用於較小的電路設計，而管線處理設計提供更高的處理效能，但是也增加了使用的面積。 本篇論文提出新的管線處理架構，這個架構是根據平行處理來實現AES的演算法，再加上本篇提出新的ShiftRow電路架構，稱之為預選型ShiftRow電路，其目的可以減少暫存器的使用；藉著平行處理和管線處理兩種架構的結合，它可以提供大約870Mbits/s的高處理速度，以及使用大約397369個較少的Gate counts。和平行架構相比，本篇提出的架構要快上50%；同時，如果和管線處理相比，本篇的架構要小20%的面積。
並列摘要
Most data transmit through the network are the form of pure document. These data were caught easily by other people. That leads some sensitive information to disclose. Encrypt is the key operation to insure data safety. AES algorithm is the process of data translates to code. It can protect data against intruder. Initially, most AES algorithms are implemented in software; however the software encryption could not follow the transmission speed. This leads to hardware design of AES where parallel processing and pipelining is possible. The hardware construction divides into parallel processing and pipeline processing roughly. The parallel processing suit to low circuit area, and the pipeline processing suit to high throughput. Thus, hardware systems offer superior throughput performance, but increase hardware area. We proposed a new pipeline FPGA implementation of AES algorithm based on the parallel architecture. In addition to, this thesis proposed a new ShiftRow circuit. This circuit is called pre-choose ShiftRow architecture. By way of combine pipeline with parallel architecture that provides high data throughput about 870Mbits/s and lower gate counts about 397369. In this thesis compared with parallel and pipeline architecture, the speed is higher 50% and the area is smaller 20%.