A Two-level Simultaneous Test Data and Time Reduction Technique for SOC

A two-level test data compression technique is presented to reduce both the test data and the test time for System on a Chip (SOC). The level one compression is achieved by Huffman coding for the entire SOC. The level two compression is achieved by broadcasting test patterns to multiple cores simultaneously. Experiments on the d695 benchmark SOC show that the test data and test time are reduced by 64% and 35%, respectively. This technique requires no change of cores and hence provides a feasible SOC test compaction solution for the SOC integrators.

並列關鍵字

test compression ； SOC testing ； test time reduction ； design for testability ； computer-aided design ； IEEE 1500

被引用紀錄

邱畊銘（2008）。嵌入式矽智財核心之IEEE 1500安全測試封套〔碩士論文，國立臺灣大學〕。華藝線上圖書館。https://doi.org/10.6342/NTU.2008.00701

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高琮評（2007）。支援全速延遲測試之IEEE 1500標準測試封套設計與驗證測試方法〔碩士論文，國立臺灣大學〕。華藝線上圖書館。https://doi.org/10.6342/NTU.2007.01062

吳柏霖（2006）。IEEE 1500標準測試封套產生和驗證及功率預估自動化工具之實現〔碩士論文，國立臺灣大學〕。華藝線上圖書館。https://doi.org/10.6342/NTU.2006.01789

Liaw, Y. T. (2005). 使用於系統晶片中之兩階層式測試資料暨測試時間壓縮 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2005.01270

國際替代計量

A Two-level Simultaneous Test Data and Time Reduction Technique for SOC

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