高介電係數金屬氧化物閘介電層在液晶薄膜電晶體之應用

Applications of High-k Gate Dielectric on Thin Film Transistors

鄭錦隆(Chin-Lung Cheng)

《真空科技》 18卷4期 (2006/02) Pp. 44-51

https://doi.org/10.29808/JVSROC.200602.0008

摘要

本文將說明高介電係數(high-k)金屬氧化物在液晶薄膜電晶體之應用，因為閘介電層(gate dielectric)品質及場效載子遷移率(mobility)為決定低溫複晶矽薄膜電晶體性能及可靠度的兩個重大因素，所以閘介電層應用於薄膜電晶體時，必須考慮介電層材料及電性的要求；採用高介電係數閘介電層可以提高汲極電流；在選擇高介電係數閘介電層材料時，應特別注意材料本身及與基板(substrate)或電極之間的特性，如能障高度、熱穩定度、界面特性、介電層結晶形態、與電極的相容性、製程間的相容性以及可靠度等。

並列摘要

In this work, the applications of high-k gate dielectric on thin-film transistors were described. Since the performances of thin-film transistors can be affected by the quality of gate dielectric and carrier mobility in channel, the material and electrical characteristics of gate dielectric need to be considered. Moreover the drain current can be increased by using the high-k gate materials as gate dielectric. The characterizations including barrier height, thermodynamic stability on Si, interface quality, dielectric film morphology, gate and process compatibility and reliability for the selection of materials for gate dielectric applications also need to be deliberated.