透過您的圖書館登入
IP:3.142.171.180
  • 期刊

應用於射頻接收機之可降頻正交電荷域濾波器

A Quadrature Charge-Domain Filter with Frequency Downconversion for RF Receivers

摘要


本論文描述一正交電荷域濾波器,此電路可以同時提供降頻濾波與正交訊號分相功能。正交電荷域濾波器在一定義的取樣頻率與一特定的輸入頻率下,其可以被使用作為正交分相器。在經由次諧波取樣與有限脈波濾波器參數的選擇,正交電荷域濾波器可以作為一降頻混波器與反假像濾波器,以利於射頻接收器應用。正交電荷域濾波器在使用1072MS/s取樣頻率下,量測結果顯示53dB的截止頻帶抑制能力,32.5dB假像頻帶拒絕能力與44MHz的工作頻寬。在正交分波功能的表現能力上,正交電荷域濾波器在訊號降頻後,解調64QAM訊號的表現可以達到-27.67dBEVM。此晶片設計使用1.2V電壓總共消耗7.7mA功率電流,晶片實現於90奈米CMOS數位製程總共消耗了0.08平方公厘晶片面積。

並列摘要


A quadrature Charge-Domain filter (QCDF) for frequency downconversion and filters is proposed. The QCDF could be a splitter by selecting the input frequency and employing a specific sampling rate. Through subsampling operation along FIR-Filter coefficients, QCDF provides a frequency downconversion and Anti-Alias filter (AAF) for RF receiver applications. After measurement of QCDF by a 1072MS/s sampling rate, chip performed a 53dB Stop-Band attenuation (SBA), a 32.5dB alias-band rejection (ABR), and 44MHz bandwidth. For quadrature performance after downconversion, this QCDF performed -27.67dB EVM upon a 64QAM signal with 54Mb/s. This chip totally consumed 7.7mA power current upon a 1.2V supply and occupied 0.08mm^2 in 90nm CMOS process.

延伸閱讀