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奈米電子元件之銅金屬化薄膜製程技術

Copper Metallization Thin-Film Fabrication Techniques for Nano-Electronic Devices

摘要


大馬士製程結合電化學析鍍與化學機械研磨已是90nm技術節點之奈米積體電路元件的標準化銅金屬內連接導線製造技術;銅因相對高的導電度與可靠度而能取代傳統的鋁基導線,而成為高解析度、超大尺寸TFT-LCD平面顯示器的連接導線。但是,矽晶(或介電層)基材表面必須先沉積一層金屬性擴散阻障層以克服銅本身的高熱擴散性與高熱應力驅使漂移率;並要在其上方生長合適的晶種層以觸發電化學銅薄膜導線的生長。本文將首先介紹“大馬士結構體”以突顯這些奈米電子、光電元件之銅金屬化製程所要求的積層薄膜及製程整合特性,接著回顧濃鍍沉積金屬性氮化物擴散阻障層的發展過程,與一些具開創性的Ta基及Ti基超薄氮化物阻障層的特性;最後將介紹另一創新性的超微細、超微密晶種生長技術,並展示全程電化學無電鍍析鍍厚度僅10nm的超薄阻障層及銅薄膜導線之製作能力。

並列摘要


Damascene process in conjunction with electrochemical plating and chemical mechanical polishing is the state of the art for the fabrication of Cu interconnects for the 90 nm technology node of nano-integrated circuits; Cu could replace the convectional Al-based alloys as interconnects for super-sized, ultra-high resolution TFT-LCD panels due to its relatively high conductivity and reliability. However, a diffusion barrier layer has to be deposited firstly on the Si (or dielectric) underlying substrate to overcome the high thermal diffusivity and biased drift velocity of Cu, and then catalytic seeds have to be put on the top to initiate the growth of Cu films using electrochemical plating. Herein, Damascene structure will be introduced firstly, highlighting the issues of integrations of both the stacked films and manufacturing processes for the Cu metallization of nano-electronic and photonic devices. Then, the evolution of sputter-deposited metallic, nitride diffusion barrier layers will be briefly reviewed, followed by an introduction of the findings of some ultrathin-designed Ta and Ti nitride based barrier layers. Finally, a seeding method, distinct from those developed previously, for the growth of ultrafine, densely populated seeds will be reported, catalyzing the fabrication of ultrathin (~ 10 nm) barrier layers using all-electrochemical featured electroless plating.

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