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環繞式閘極奈米線電晶體之飄移穩定性研究

Study of Drift Stability on Gate-All-Around Nanowire Transistors

摘要


本研究製作通道厚度約為7奈米、寬度約為80奈米的無接面(Junctionless)及反轉式(Inversion Mode)矽環繞式閘極奈米線電晶體。我們討論環繞式閘極在不同電壓控制下,兩種奈米線電晶體的長時間飄移電流穩定性,並建立於生物感測元件應用的可能工作區。電性量測顯示無接面矽環繞式閘極奈米線電晶體,擁有極佳的電性;陡峭的次臨界擺幅(SS; 63mV/dec),極低的汲極引發位能障(DIBL; 10±3 mV/V)和高開\關電流比(~5×10^6, V_D=0.1 V, V_G=1 V)。另一方面,由於Volume Inversion效應,無接面矽環繞式閘極奈米線電晶體顯示優異的載子遷移率,約反轉式矽環繞式閘極奈米線電晶體2倍大,也正因較低的載子表面散射,元件操作在不同閘極電壓時,有著較低的背景雜訊和較佳的飄移穩定性;平均飄移電位在線性區(V_G=1 V)為14.17±1.04 mV,近飽和區(V_G=0 V)為2.62±2.17 mV,次臨界區(V_G=-0.47 V, I_D= 1nA)為0.45±0.25 mV。

並列摘要


In this work, we characterized both junctionless (JL) and inversion mode (IM) gate-all-around (GAA) nanowire field-effect transistor (NWFET), and discussed drift current stability for both devices at different Gate-Voltage regimes in a long-time operation for potential bio-sensing applications. JL-NWFET exhibited very high performance in electrical properties including a very steep subthreshold slope (SS; 63mV/dec), a virtual absence of drain-induced barrier lowering (DIBL; 10±3 mV/V), and a high ON/OFF current ratio ~5×10^6 (V_D=0.1 V, V_G=1 V). Due to the volume inversion effect that reduces the surface scattering, the JL GAA NWFET exhibits better carrier mobility, and the transconductance (Gm) is approximately two times larger than that of IM GAA NW FET device. JL device also presents lower background noise and a smaller drift in different operation regions; an average drift potential of 14.17±1.04 mV in linear regime (V_G=1 V), 2.62±2.17 mV in near saturation (V_G=0 V), 0.45 mV±0.25 in subthreshold regime (V_G=-0047 V, 1_D= 1 nA).

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