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An Efficient Power-Saving Scheduling Algorithm

並列摘要


Dynamic voltage and frequency scaling to reduce power consumption in embedded systems is a promising research domain. Most of these approaches usually use the ratio between the deadline of a task and the worst case execution time of the task to modify the processor's operating frequency. As a result, an analysis of the given application must be conducted to obtain some parameters for the algorithm. Since countless applications are available for portable devices, it is difficult to implement these approaches on portable devices. To deal with these issues, an efficient algorithm for reducing power consumption that can be easily implemented on an actual hardware device is presented. The proposed algorithm combines priority-based scheduling and earliest deadline first scheduling to schedule real-time tasks and normal tasks. It then uses a periodic routine to check whether the system has satisfied any conditions that require it to modify the operating mode. The experiment results show that the proposed algorithm can reduce energy consumption by up to 45.1%.

被引用紀錄


Yang, S. H. (2009). Analyzing VoIP Capacity with Delay Guarantee for Integrated HSPA Networks [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-1111200916110919
Wu, C. Y. (2014). 於正交分頻多重進接網路中最大化處理能力與省電效益之下行頻寬分配最佳化之研究 [doctoral dissertation, National Chung Cheng University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0033-2110201613592823

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