高輸出擺幅摺疊式運算放大器之設計與實作

Design and implementation of High Output Swing Folded Cascode OP Amplifier

李民慶(Min-Chin Lee) ； 王清松(Ching-Song Wang) ； 黃鈞毅(Jun-Yi Huang) ； 陳琨元(Kun-Yuan Chan) ； 游育銘(You-Ming Yo) ； 李霈穎(Pei-Ying Lee)

《亞東學報》 29期 (2009/06) Pp. 71-80

https://doi.org/10.30167/JOIT.200906.0009

摘要

CMOS運算放大器乃組成多數混合訊號積體電路之核心單元，本文針對設計組成一高性能OPA之基本單元：參考偏壓電流源電路，輸入差動放大器與源級退化之共源極放大器之設計考量加以分析，最後利用TSMC-0.35umCMOS製程技術完成模擬與設計一具高輸出擺幅(3.2V)、高單增益頻寬(14.6MHz)、高共模拒斥比(92dB)、高電源漣波拒斥比(90dB)與高迴轉率(14.85V/us)等操作條件且穩定(PM=53.8°)之摺疊疊接式運算放大器。

關鍵字

摺疊疊接放大器 ； 單增益頻寬 ； 迴轉率 ； 輸出擺幅 ； 相角邊限

並列摘要

CMOS Operational Amplifier (OPA) is main sub-structure of mixed-mode integrated circuit system in nowadays. In this paper, the main components high performance OPA consist of the basic bias reference current circuits, input differential amplifier and common-source with source degeneration stage are analyzed and discussed in detail. The proposed high output swing folded cascoded OPA with a chip area of 0.468×0.468mm^2 is designed and fabricated in a 2P4M TSMC 0.35-um CMOS process. And experimental results show that the OPA is well stable (phase margin about 53.8), with 3.2V output swing, unit-gain bandwidth (14.6MHz), 92dB CMRR, 90dB PSRR and 14.85V/us slew rate performances.

並列關鍵字

Folded Cascode Amplifier ； Unit-gain Bandwidth ； Slew Rate ； Output Swing ； Phase Margin

參考文獻

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