Structural Design for a 1.6 Kbps GELP Speech Coder

1.6Kbps GELP語音編解碼器之結構設計

胡懷祖(Hwai-Tsu Hu) ； 陳泳男(Yong-Nan Chen)

《國立宜蘭大學工程學刊》 3期 (2007/02) Pp. 69-85

https://doi.org/10.6176/BCE.2007.03.16

摘要

本文針對低位元率語音編碼之硬體實現提出結構性設計，負責程序處理之演算法源自於傳統的脈衝激源線性預測語碼器，另掺入聲源之特性。為了讓編解碼演算法得以硬體實作，諸如計算模組的複雜度與算數運算的需求均加上許多限制，然而簡化後的演算法仍能執行1.6Kbps語音編解碼並輸出可接受之音質。我們藉由多樣設計工具，經歷了演算修正、定點數分析、硬體設計、電路合成等過程，最後以Verilog硬體描述語言設計出之電路硬體是在擁有FPGA的DSP開發板進行編譯及驗證，所得結果證實這套架構的工作效能。由於該架構不需耗用過多硬體資源，其實是非常適合以單晶片實現。

關鍵字

語音編解碼 ； VLSI構造 ； 硬體實現

並列摘要

This paper presents a structural design for hardware implementation of low-bit-rate speech coding. The processing algorithm emerges from the traditional pitch-excited linear prediction vocoder with incorporation of glottal-source properties. To make the coding algorithm realizable, constraints are imposed on the complexity of computational modules as well as the need of arithmetic operations. Nonetheless, the simplified algorithm is still capable of carrying out 1.6Kbps speech coding with acceptable quality.We have gone through algorithm modification, fixed-point analysis, hardware design, and circuit synthesis by making use of various design tools. The hardware design, described by using Verilog-HDL, is compiled and verified on an FPGA-based DSP board. Our results confirm that the proposed architecture works quite well. As this architecture needs not consume many hardware resources, it is suitable for single chip implementation.

並列關鍵字

speech coding ； VLSI architecture ； hardware implementation