具平行運算之高精準距離時間轉換電路暨整合SPAD前端感測器與自動清除信號之光達系統晶片設計

Parallel-Process Auto-Clear Time-to-Digital Converter Chip Integrated with Single-Photon Avalanche Diode Sensors for a Light Detection and Ranging System

謝宜蓁(YI-CHEN HSIEH)

《科學與工程技術期刊》 18卷2期 (2022/09) Pp. 17-25

摘要

本篇論文提出使用兩組TDC進行並行計算處理，以提高整體TDC的計算速度，減少其死亡時間，並同時保持高解析度的能力。將前端光學感測器－SPAD與TDC整合於同一顆晶片中，以加快TDC與SPAD之間的信號傳輸，減少延遲時間。藉由上述方式，數據傳輸速度將大大提高，帶來高性能的光學雷達系統。本篇採用TSMC-T18HVG2製程實現晶片設計。參考時脈頻率為100MHz。整體TDC的最短死亡時間為20ns，最高解析度為100ps，量測範圍可達382.5公尺，晶片面積為2.5 mm^2。

關鍵字

光學雷達系統 ； 時間數位轉換器 ； 單光子雪崩二極體

並列摘要

This study proposes parallel computer processing on two groups of time-to-digital converter (TDC) chips to improve the calculation speed of the overall TDC, reduce its death time, and simultaneously maintain high-resolution capability. Integrating a single-photon avalanche diode (SPAD) and a TDC on the same chip can speed up the TDC input and SPAD output transmission, reducing the signal transmission delay. In the proposed design, the front-end SPAD optical sensor and TDC circuit are integrated, and the TSMC-T18HVG2 process is employed. The reference clock frequency is 100 MHz. The TDC's shortest dead time is 20 ns, its resolution is 100 ps, the measurement range can reach 382.5 m, and the chip area is 2.5 mm^2. Two TDCs can operate simultaneously, significantly improving the data transmission speed and giving a light detection and ranging system high-performance.

並列關鍵字

LiDAR system ； time to digital converter ； single photon avalanche diode

參考文獻

Cheng, C. H., C. K. Chao, K. C. Yeh, D. G. Liu and S. D. Lin (2021) The Performance-Complexity Efficient Time-to-Digit and Data-Processing Chips Design and Validation for a LiDAR System. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-4). IEEE.

Niclass, C., M. Soga, H. Matsubara, M. Ogawa and M. Kagami (2013) A 0.18- μ m CMOS SoC for a 100-m-Range 10-Frame/s 200 × 96-Pixel Time-of-Flight Depth Sensor. IEEE Journal of solid-state circuits, 49(1), 315-330.

Yoshioka, K., H. Kubota, S. Kondo, T. T. Ta, H. Okuni, K. Watanabe, M. Hirono, Y. Ojima, K. Kimura, S. Hosoda, Y. Ota, T. Koizumi and N. Kawabe, et al. (2018) A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240×96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. IEEE Journal of Solid-State Circuits, 53(11), 3026-3038