具記憶體使用效率之低功率低密度同位元查核解碼器設計

A Memory-Efficient Layered QC-LDPC Decoder

湯雲欽(Yun-Ching Tang) ； 姚長昆(Chang-Kun Yao) ； 林泓均(Hong-Chin Lin)

《修平學報》 27期 (2013/09) Pp. 145-153

摘要

本文提出了一個簡化的分層最小值－總和演算法（LMSA），以便設計與實作類循環－低密度同位元查核（QC-LDPC）解碼器。此解碼器結構可以輕鬆的容納一個解碼分層，同時可以使重複解碼的次數減少，而達到與之前相似的解碼效能。所提出的LMSA架構，由於簡化資料的位元數，在較長的編碼中可以減少許多記憶體的使用。本文所設計之解碼器碼長為4608位元且碼率是8/9，使用台積電90奈米互補式場效電晶體技術合成，在頻率為110MHz，解碼傳輸率可達到3.96Gbps，比起傳統之LMSA，只需約三分之一的記憶體使用量。

關鍵字

類循環 ； 低密度同位元查核 ； 解碼器 ； 分層最小值－總和演算法 ； 記憶體

並列摘要

In this paper, a simplified layered min-sum algorithm (LMSA) is proposed to design and implement quasi-cyclic low density parity check (QC-LDPC) decoder. This decoding architecture can easily accommodate a decoding layer and reduce the number of iterations to achieve the similar decoding performance. Owing to the reduced quantization bits of data information, the proposed LMSA decoder significantly reduces the memory requirement for long codes. Here, the decoder with code length of 4608 and coding rate of 8/9 was synthesized using TSMC 90nm CMOS technology. The throughput is 3.96Gb/s at 110MHz with only 1/3 memory requirement compared to the conventional LMSA decoder.

並列關鍵字

quasi-cyclic ； low density parity check (LDPC) ； decoder ； layered min-sum algorithm (LMSA) ； memory

參考文獻

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