無線光纖傳輸系統中多碼率低密度同位元查核碼解碼器之實作與研究

Implementation and Study of Multi-Rate LDPC Decoders in Radio-Over-Fiber Systems

湯雲欽(Yun-Ching Tang) ； 蕭家州(Chia-Chou Hsiao) ； 林泓均(Hong-Chin Lin)

《修平學報》 27期 (2013/09) Pp. 187-199

摘要

本論文提出應用於16-QAM之無線光載射頻通道（Radio over Fiber，ROF）之多碼率LDPC解碼器VLSI設計與實作。本主題有幾個主要的重點：（1）.建構三個分割轉移LDPC Code（Partition and Shift LDPC，PS-LDPC），其查核矩陣分別為（480，2400）、（800，2400）以及（480，4800），碼率分別是4/5、2/3以及9/10，其Girth分別為8、6、6，三者都具有優秀的更正能力。（2）.利用化簡後的Layered Min Sum Algorithm搭配LLR數值量化擴增的方式，在硬體複雜度不高的同時，亦能達到良好的效能。（3）.LDPC解碼器架構採用雙路徑部分平行式架構，在切管線使頻率上升的同時，亦不造成電路閒置的情形，使傳輸率倍增。（4）.三個查核矩陣盡量共用硬體，包括計算單元與暫存器的硬體共用技巧，來減少所需耗費的面積。使用聯華電子UMC 90nm CMOS技術實作後，晶片核心面積為8.19mm^2，在電壓供應0.9伏特時，最高工作頻率為110MHz。固定解碼次數8次下，此三個查核矩陣（480，2400）、（800，2400）、（480，4800）所對應的傳輸率分別為5.5Gbps、3.3Gbps、2.75Gbps，其功率消耗分別為332.7mW、339.5mW、368.6mW。

關鍵字

低密度同位元查核 ； 解碼器 ； 分層最小值－總和演算法 ； 記憶體

並列摘要

In this thesis, VLSI implementation of a multi-rate low-density parity-check (LDPC) decoder used in 16-QAM Radio over Fiber (ROF) channel is presented with four important features. The first is constructing three Partition and Shift LDPC (PS-LDPC) Codes with the parity check matrices (H) of (480, 2400), (800, 2400) and (480, 4800) corresponding to the coding rates of 4/5, 2/3, 9/10, and girths of 8, 6, 6, respectively. Secondly, good performance was achieved by a modified Layered Min Sum algorithm using quantization expansion of log likelihood ratio for less hardware complexity. The third is the proposed dual path partial parallel architecture using pipeline can increase the operating frequency, and double the throughput with the little circuit overhead. The last feature is the three LDPC codes share the hardware as much as possible, including the computing units and registers to reduce the chip area. Using the UMC 90nm COMS technology, the maximum frequency reaches 110MHz with the core area of 8.19mm2 at supply voltage of 0.9V. With 8 iterations per decoding process, the throughputs of PS-LDPC codes (480, 2400), (800, 2400) and (480, 4800) are 5.5Gbps, 3.3Gbps, 2.75 Gbps with the power consumptions of 332.7mW, 339.5mW and 368.6mW, respectively.

並列關鍵字

low density parity check (LDPC) ； decoder ； layered min-sum algorithm (LMSA) ； memory

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