VHDL Modelling of Reed Solomon Decoder

In digital communication systems, both random and burst errors may occur in the transmission channel. As a result, the signal will be distorted at the receiver. Error correction coding is required to eliminate such errors. In this study, a Reed Solomon (255, 191) error correction code is modelled to detect and correct the data transmitted in a noisy channel. Reed Solomon (RS) codec is a powerful error correction tool that is used to ensure the errors correction in digital communication systems. However, RS codec is computionally intensive and custom design is required for different digital systems. RS decoder modeling using Very High speed hardware Description Language (VHDL) made it suitable to be implemented on a Field Programmable logic Array (FPGA) based copocessor. The flexibility of FPGA in hardware reconfiguration greatly reduces the development time for RS decoder in all kinds of specialized circuit designs. The arithmetic operations which are used in RS code were Galois Fields (GF) addition and multiplication. This study presented: i) RS encoder modelled using MATLAB with data encoded in the noisy channel for functional verification. ii) RS decoder modelled in Very High speed hardware Description Language (VHDL) to recover the erroneous data. RS decoder has been successfully simplified to only four sub-modules in order to reduce the FPGA’s resources utilization. The VHDL modelled RS (255, 191) decoder has the capability of 32 symbol-errors detection and correction. It can be added into the VHDL designer library for future system designs.

並列關鍵字

Error correction code ； FPGA ； signal interference

國際替代計量

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